clock-domains
There are 5 repositories under clock-domains topic.
hdl-util/clock-domain-crossing
Utilities for clock-domain crossing with an FPGA
w-tr/clock-domain-crossing
In digital design, it is sometimes necessary to transfer data from one clock domain to another. However because of the nature of how data is stored, there is a probability the transaction will have a setup and hold violation or data is lost because of the different between the domain speeds.
zslwyuan/Hi-ClockFlow
Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis
MarleyLobao/UVM-mult-clk-domain
Through a verification environment, this repository uses UVM to handle with multiple clock domains and virtual sequences.