PyHDI/veriloggen

Issues

• Jupyter notebook 'hello_led.ipynb'

  #62 opened 2 months ago by zehonyi21
  0

• Java runtime error

  #61 opened 7 months ago by VPIgnite99
  0

• # The task call part in veriloggen library is not generated correctly

  #60 opened 8 months ago by Hikakkun
  0

• Multi instance using the same module

  #57 opened a year ago by panwenzong
  5

• read_verilog_module does not support instances with unconnected ports, will generate a TypeError.

  #58 opened a year ago by darcy-wu
  0

• typo in stream/stypes.py line 52

  #52 opened 2 years ago by mayagokhale
  1

• Imcompatibility of `Module.Wire` and `Module.TmpWire` regarding the keyword arguments.

  #49 opened 2 years ago by estodi
  1

• Convention violation of AXI Lite protocol on AxiLiteSlave

  #50 opened 2 years ago by RyusukeYamano
  1

• `types.AxiMaster` should be have a cap of number of outstanding readout transactions.

  #51 opened 2 years ago by RyusukeYamano
  1

• Slice in Wire with two dimension

  #47 opened 3 years ago by LucasBraganca
  1

• Creating a combinational sequence

  #46 opened 3 years ago by kiteloopdesign
  0

• Case statement within combinational block

  #45 opened 3 years ago by kiteloopdesign
  2

• to_verilog("file.v") creates two empty lines at beginning of file

  #44 opened 3 years ago by kiteloopdesign
  0

• Creating input with literal BW in the form of [n:0] instead of [n-1:0]

  #43 opened 3 years ago by kiteloopdesign
  0

• Support for SystemVerilog Interfaces

  #42 opened 3 years ago by kiteloopdesign
  2

• always @ ( * ) combinational block

  #41 opened 3 years ago by kiteloopdesign
  2

• deleted

  #40 opened 4 years ago by shtaxxx
  0

• stream.source with only size without data read

  #39 opened 4 years ago by shtaxxx
  0

• Bug of stream.ReduceDiv for signed values

  #38 opened 4 years ago by shtaxxx
  0

• Inserting user-defined simulation code for Verilator mode

  #37 opened 4 years ago by shtaxxx
  0

• Infinite read size for stream.source

  #36 opened 4 years ago by shtaxxx
  0

• Explicit latency constraint between two stream objects which accesses to external resources outside of the stream.

  #32 opened 4 years ago by shtaxxx
  1

• Indirect access RAM in Veriloggen.Thread.Stream

  #17 opened 4 years ago by shtaxxx
  1

• Travis CI -> CircleCI?

  #23 opened 6 years ago by shtaxxx
  4

• memcpy between on-chip RAMs

  #25 opened 4 years ago by shtaxxx
  1

• Supporting indirect addressing by sink RAM of Thread.Stream

  #27 opened 4 years ago by shtaxxx
  1

• Supporting AXI Stream interface

  #21 opened 4 years ago by iitaku
  3

• Supporting explicit Block RAM generation

  #22 opened 5 years ago by iitaku
  1

• Supporting multiple outstanding DMA requests

  #26 opened 5 years ago by shtaxxx
  1

• Online tutorial on binder/jupyter

  #24 opened 6 years ago by shtaxxx
  0

• Better Documentation/Tutorials

  #19 opened 6 years ago by xd009642
  6

• How to use from_verilog function in veriloggen

  #20 opened 6 years ago by bhargav3333
  1

• Help with design of low-level HDL language

  #18 opened 6 years ago by XVilka
  1

• realtime monitoring of simulation output

  #16 opened 7 years ago by sgherbst
  1

• iverilog libdir option

  #15 opened 7 years ago by sgherbst
  1

• Untimed mode (no clock-level FSM) of Thread for simulation

  #8 opened 9 years ago by shtaxxx
  0

• Help, how to make a verilog module from a Boolean expression

  #14 opened 7 years ago by LucasBraganca
  4

• Type check

  #2 opened 7 years ago by shtaxxx
  1

• While statement

  #12 opened 9 years ago by shtaxxx
  1

• Initial statement

  #1 opened 9 years ago by shtaxxx
  1

• A stub for importing a Verilog module.

  #4 opened 9 years ago by shtaxxx
  1

• Generate statement (genvar, generate)

  #6 opened 9 years ago by shtaxxx
  1

• Bit concatenate { AAA, BBB, CCC } and { AAA {XX'hYY} }

  #11 opened 9 years ago by shtaxxx
  1

• Bit truncation [XXX:YYY]

  #9 opened 9 years ago by shtaxxx
  1

• Pointer [XXX]

  #10 opened 9 years ago by shtaxxx
  1

• function statement

  #7 opened 9 years ago by shtaxxx
  1

• Module generation on Instantiation

  #3 opened 9 years ago by shtaxxx
  1

• Python PLI support for simulation

  #5 opened 9 years ago by shtaxxx
  0