verilog-hdl
There are 499 repositories under verilog-hdl topic.
VUnit/vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
ultraembedded/cores
Various HDL (Verilog) IP Cores
PyHDI/Pyverilog
Python-based Hardware Design Processing Toolkit for Verilog HDL
sudhamshu091/32-Verilog-Mini-Projects
Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM
NNgen/nngen
NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
PyHDI/veriloggen
Veriloggen: A Mixed-Paradigm Hardware Construction Framework
mshr-h/vscode-verilog-hdl-support
HDL support for VS Code
dpretet/async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
ultraembedded/core_jpeg
High throughput JPEG decoder in Verilog for FPGA
Gowtham1729/Image-Processing
Image Processing Toolbox in Verilog using Basys3 FPGA
AUCOHL/Fault
A complete open-source design-for-testing (DFT) Solution
neelkshah/MIPS-Processor
5-stage pipelined 32-bit MIPS microprocessor in Verilog
thedatabusdotio/fpga-ml-accelerator
This repository hosts the code for an FPGA based accelerator for convolutional neural networks
aptx1231/BUAA_CO
2017级北航计算机学院计算机组成原理课程设计(MIPS CPU)
gupta409/Processor-UVM-Verification
System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
ben-marshall/uart
A simple implementation of a UART modem in Verilog.
Jed-Z/computer-organization-lab
中山大学计算机组成原理实验 (2018 秋)：用 Verilog 设计并实现的简易单周期和多周期 CPU
bojackchen/digital-flow
This is a tutorial on standard digital design flow
Michaelvll/RISCV_CPU
A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL
snbk001/Verilog-Design-Examples
Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous FIFO, 8x8 Sequential Multiplier
maxs-well/Ethernet-design-verilog
Gigabit Ethernet UDP communication driver
michaelehab/AES-Verilog
Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
RuSys/Verugent
Verilog generation tool written in Rust
tomtor/HDL-deflate
FPGA implementation of deflate (de)compress RFC 1950/1951
ashishrana160796/verilog-starter-tutorials
Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.
mongrelgem/Verilog-Adders
Implementing Different Adder Structures in Verilog
defparam/higan-verilog
This is a higan/Verilator co-simulation example/framework
halftop/Interface-Protocol-in-Verilog
Interface Protocol in Verilog
TheSUPERCD/8bit_MicroComputer_Verilog
This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.
jfoshea/Viterbi-Decoder-in-Verilog
An efficient implementation of the Viterbi decoding algorithm in Verilog
Arjun-Narula/Traffic-Light-Controller-using-Verilog
the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.
metr0jw/Spiking-Neural-Network-on-FPGA
Leaky Integrate and Fire (LIF) model implementation for FPGA
lightcode/8bit-computer
A simple 8-bit computer build in Verilog.
mihir8181/VerilogHDL-Codes
Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.
maxs-well/LMS-sound-filtering-by-Verilog
LMS sound filtering by Verilog
ekb0412/100DaysofRTL
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado