verilog-hdl
There are 708 repositories under verilog-hdl topic.
ultraembedded/cores
Various HDL (Verilog) IP Cores
VUnit/vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
PyHDI/Pyverilog
Python-based Hardware Design Processing Toolkit for Verilog HDL
dpretet/async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
NNgen/nngen
NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network
mshr-h/vscode-verilog-hdl-support
HDL support for VS Code
PyHDI/veriloggen
Veriloggen: A Mixed-Paradigm Hardware Construction Framework
ultraembedded/core_jpeg
High throughput JPEG decoder in Verilog for FPGA
Gowtham1729/Image-Processing
Image Processing Toolbox in Verilog using Basys3 FPGA
AUCOHL/Fault
A complete open-source design-for-testing (DFT) Solution
thedatabusdotio/fpga-ml-accelerator
This repository hosts the code for an FPGA based accelerator for convolutional neural networks
ben-marshall/uart
A simple implementation of a UART modem in Verilog.
snbk001/Verilog-Design-Examples
Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous FIFO, 8x8 Sequential Multiplier
neelkshah/MIPS-Processor
5-stage pipelined 32-bit MIPS microprocessor in Verilog
michaelehab/AES-Verilog
Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
gupta409/Processor-UVM-Verification
System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
aptx1231/BUAA_CO
2017级北航计算机学院计算机组成原理课程设计(MIPS CPU)
ekb0412/100DaysofRTL
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
Jed-Z/computer-organization-lab
中山大学计算机组成原理实验 (2018 秋)：用 Verilog 设计并实现的简易单周期和多周期 CPU
mirseo/JSilicon
JSilicon: A dual-mode 8-bit CPU core designed entirely from scratch by an AI major during mandatory military service in South Korea. This open-source Verilog project proves that real silicon design — from ALU to CPU architecture — is possible even under the most extreme constraints.
Michaelvll/RISCV_CPU
A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL
metr0jw/Event-Driven-Spiking-Neural-Network-Accelerator-for-FPGA
FPGA based Leaky Integrate and Fire (LIF) neuron model accelerator for PyTorch
lightcode/8bit-computer
A simple 8-bit computer build in Verilog.
maxs-well/Ethernet-design-verilog
Gigabit Ethernet UDP communication driver
bojackchen/digital-flow
This is a tutorial on standard digital design flow
mongrelgem/Verilog-Adders
Implementing Different Adder Structures in Verilog
tomtor/HDL-deflate
FPGA implementation of deflate (de)compress RFC 1950/1951
ashishrana160796/verilog-starter-tutorials
Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.
RuSys/Verugent
Verilog generation tool written in Rust
TheSUPERCD/8bit_MicroComputer_Verilog
This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This project was developed as a Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.
jfoshea/Viterbi-Decoder-in-Verilog
An efficient implementation of the Viterbi decoding algorithm in Verilog
Weiyet/RTLStructLib
RTL data structure
defparam/higan-verilog
This is a higan/Verilator co-simulation example/framework
halftop/Interface-Protocol-in-Verilog
Interface Protocol in Verilog
Arjun-Narula/Traffic-Light-Controller-using-Verilog
the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.
maxs-well/ad7606-driver-verilog
AD7606 driver verilog