/100DaysofRTL

"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

Primary LanguageVerilogApache License 2.0Apache-2.0

100DaysofRTL

Hi👋, I'm Ekansh Bansal, and I'm currently immersing myself in the world of VLSI🎯, focusing on RTL design using Verilog HDL. My goal is to learn RTL within 1️⃣0️⃣0️⃣ days, and I rely on Xilinx Vivado 2022.2 Design Suite🚀 for synthesizing and simulating RTL codes👨🏼‍💻. This powerful tool💪🏼 allows me to efficiently develop complex digital circuits, including FPGAs and ASICs. I'm excited about my journey and the potential it holds for equipping me with valuable skills that I can apply to real-world problems in the future.

Here is the list of Day wise RTL Codes:-
Day: 1-> Behavioral Modeling Style

Day: 2-> Structral Modeling Style

Day: 3-> Gate Level Modeling Style

Day: 4-> Switch Level Modeling Style
Day: 5-> Universal Logic Gates using Switch Level Modeling

Day: 6-> Even Parity Generator and Checker

Day: 7-> Half Adder & Full Adder

Day: 8-> Half Subtractor & Full Subtractor

Day: 9-> Half Adder, Full Adder, Half Subtractor, Full Subtractor using Nand Gate

Day: 10-> 4 bit Parallel Adder

Day: 11-> 4 bit Adder cum Subtractor

Day: 12-> Carry Look Ahead Generator

Day: 13-> Carry Select Adder

Day: 14-> Carry Skip Adder

Day: 15-> 4 bit Multiplier

Day: 16-> 4 bit Divider

Day: 17-> N bit Comparator

Day: 18-> Multiplexer [2:1]

Day: 19-> [4:1] Mux using [2:1]

Day: 20-> Basic Logic Gates using Mux

Day: 21-> Universal Logic Gates using Mux

Day: 22-> Special Logic Gates using Mux

Day: 23-> Full Adder using Mux

Day: 24-> DeMultiplexer [1:2]

Day: 25-> DeMultiplexer[1:8] using [1:2]

Day: 26-> Basic Logic Gates using Dmux

Day: 27-> Universal Logic Gates using Dmux

Day: 28-> Special Logic Gates using Dmux

Day: 29-> Encoder [8:3]

Day: 30-> Priority Encoder

Day: 31-> Decoder [3:8]

Day: 32-> Basic Logic Gates using Decoder

Day: 33-> Universal Logic Gates using Decoder

Day: 34-> Special Logic Gates using Decoder
Day: 35-> N bit number Square [N -> N^2]

Day: 36-> Input Majority Circuit [7 input]

Day: 37-> Binary to Gray code Converter

Day: 38-> Gray code to Binary Converter

Day: 39-> Binary to 2's Complement Converter

Day: 40-> Binary to BCD Converter

Day: 41-> BCD to Excess-3 code Converter

Day: 42-> BCD to 7-Segment Converter

Day: 43-> Booth's Multiplication Algorithm

Day: 44-> Vedic Multiplier [2×2]

Day: 45-> Vedic Multiplier [4×4] using [2×2]
Day: 46-> Asynchronous and Synchronous Reset

Day: 47-> SR Latch

Day: 48-> JK Flip Flop

Day: 49-> D Flip Flop

Day: 50-> T Flip Flop

Day: 51-> SR flip flop using JK, D, T flip flops

Day: 52-> JK flip flop using SR, D, T flip flops

Day: 53-> D flip flop using SR, JK, T flip flops

Day: 54-> T flip flop using SR, JK, D flip flops

Day: 55-> Dual Edge Triggered Flip Flop
Day: 56-> Serial in Serial out (SISO) Register

Day: 57-> Serial in Parallel out (SIPO) Register

Day: 58-> Parallel in Serial out (PISO) Register

Day: 59-> Parallel in Parallel out (PIPO) Register

Day: 60-> Linear Feedback Shift Register (LFSR)

Day: 61-> Universal Shift Register

Day: 62-> Barrel Shifter
Day: 63-> Mod-N Counter

Day: 64-> Specific Sequence Counter

Day: 65-> Up/Down Counter

Day: 66-> Ring Counter

Day: 67-> Johnson Couter

Day: 68-> Gray Counter
Day: 69-> Clock Phasing

Day: 70-> Clock Edge Detector

Day: 71-> Frequency Divider {even}

Day: 72-> Frequency Divider {odd}

Day: 73-> Frequency Divider {decimal}
Day: 74-> One-HOT FSM(finite state machine)

Day: 75-> FSM Mealy_Overlapping

Day: 76-> FSM Mealy_Non-Overlapping

Day: 77-> FSM Moore_Overlapping

Day: 78-> FSM Moore_Non-Overlapping

Day: 79-> Two sequence detector using FSM
Day: 80-> Single Port RAM

Day: 81-> Dual Port RAM

Day: 82-> ROM [15*15]
Day: 83-> Arithmetic Logic Unit (ALU)

Day: 84-> Checking if Number is an Even or Odd Number

Day: 85-> Checking if Number is a Prime Number

Day: 86-> Checking if Number is a Pallindrome Number

Day: 87-> Checking if Number is an Armstrong Number

Day: 88-> Factorial of a Number

Day: 89-> Square Root and Cube Root of a Number
Day: 90-> Trafic Light Controller via FSM

Day: 91-> Printing Star and Number Patterns

Day: 92-> Highest Common Factor (HCF)

Day: 93-> Synchronous FIFO(First In First Out)

Day: 94-> Synchronous LIFO(Last In First Out)

Day: 95-> PWM (Pulse Width Modulation)

Day: 96-> Vending Machine

Day: 97-> Car Parking Management System

Day: 98-> Sine Wave Generator

Day: 99-> Error Detection and Correction using Hamming Code Technique

Day: 100-> Serial Port Interface (SPI)