ekb0412
Currently pursuing Bachelor of Technology in Electronics and communication from GLA University Mathura. Skilled in Communication, Teamwork, VLSI Design, Cadence
GLA University Mathura
Pinned Repositories
1-bit_6T_SRAM
This repository contains the analysis and simulation of 6T SRAM using Cadence Virtuoso EDA on different technology nodes (45nm, 90nm, 180nm) and some leakage reduction technique.
100DaysofRTL
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
ekb0412
Main Repository
UART-Serial-Port-Module-Design-Main-ASIC-
This repository contains a project on a VLSI Front-End design (UART) using Verilog HDL
ekb0412's Repositories
ekb0412/100DaysofRTL
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
ekb0412/ekb0412
Main Repository
ekb0412/1-bit_6T_SRAM
This repository contains the analysis and simulation of 6T SRAM using Cadence Virtuoso EDA on different technology nodes (45nm, 90nm, 180nm) and some leakage reduction technique.
ekb0412/UART-Serial-Port-Module-Design-Main-ASIC-
This repository contains a project on a VLSI Front-End design (UART) using Verilog HDL