vlsi-design
There are 121 repositories under vlsi-design topic.
limbo018/Limbo
Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
meiniKi/FazyRV
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
ekb0412/100DaysofRTL
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
twweeb/VLSI-Physical-Design-Automation
Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
tharunchitipolu/Dadda-Multiplier-using-CSA
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
zhangmozhe/microshift_compression
Microshift Compression: An Efficient Image Compression Algorithm for Hardware
hibagus/64pointFFTProcessor
Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
srohit0/mida
Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"
synogate/gatery
Gatery, a library for circuit design.
maazm007/vsdsquadron-mini-internship
VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.
mihir8181/VLSI-Design-Digital-System
This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details
paripath/cdf
Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format
zwhexplorer/Spiking-Neural-Network-Accelerator-EE552-project
Spiking Neural Network Accelerator
lip6/alliance-check-toolkit
Tutorial, examples and regression tests for Coriolis & Alliance (LIP6)
efabless/ravenna
32-bit RISC-V microcontroller
ChrisShakkour/RV32I-MAF-project
Designinig a Pipeline in-order 5 stage RISC-V core RV32I-MAF
krutideepanpanda/RISC-V-based-micro-controller-using-OpenLane
This is part of EC383 - Mini Project in VLSI Design.
maazm007/100Daysof_RTL
The Repository contains the code of various Digital Circuits
Electro-SPY/Phase-Locked-Loop
We are designing a CP-PLL. The following link provides resources about PLL design.
mnmhdanas/UART-protocol
UART - RTL Design and Verification
rohankalbag/vlsi-design
VLSI Design - Autumn Semester 2022 - Indian Institute of Technology Bombay
karthik-r-rao/VLSI_Physical_Design_Tool
A simple tool to demonstrate the physical design steps of VLSI Design Flow.
Sooryakiran/Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project
Domain Specific Hardware Accelerators - VLSI CAD Project
VardhanSuroshi/VLSI-ASIC-Design-Flow
This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
iamraufu/BRACUCSE460
VLSI Design - Spring 2022
neeraj1397/A-Primer-For-Physical-Design-Automation
This repository contains python code snippets that implement several algorithms for automating the VLSI Physical Design process. This is based on the learnings from the course - EE5333W (Introduction to Physical Design Automation) at IITM.
Vishakha7501/Sky-130-RTL-Design-and-Synthesis-Workshop-using-Verilog
RTL Design and Synthesis Workshop using Verilog with Sky130 Technology
mehadihn/BRACUCSE460
BRACU CSE460 Lab (Summer 2020)
pankajpatro703/spicey-ckts
NGspice netlist files for simulation of analog and digital circuits.
sagniknitr/VLSI-Lab-Final-Year-Undergraduate-
This respositort contains all vhdl codes and simulations of final year vlsi lab of NIT Rourkela
synogate/gatery_template
Template project for using gatery
ads930/4_bit_adder
This is a 4-bit pipelined carry-ripple adder. The design has been optimized for delay. To view the project, download the zip file and open the project in Cadence Virtuoso.
aesthet1c0der/Verilog-projects
ALU (Arithmetic and Logic Unit), Ripple carry adder, Half adder and full adder are designed using all 3 styles (structural, behavioral, dataflow) and tested by generating stimulus using testbench
harsh-kmr/verilog_experiments
This repository is created for VLSI Experiments in Verilog for Engineering Sem 5 based on the Syllabus of IIIT Trichy. Here you can find the necessary codes, design files, and documentation for the experiments
sidhantp1906/RTC-Real-Time-Clock-
Design of real time clock(RTC) using Verilog HDL
Valendrew/vlsi-design
Combinatorial and Decision Making Optimization (CDMO) project during the A.Y. 2021/2022.