vlsi-design
There are 176 repositories under vlsi-design topic.
limbo018/Limbo
Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
meiniKi/FazyRV
A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
ekb0412/100DaysofRTL
"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
twweeb/VLSI-Physical-Design-Automation
Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
RarityBrown/ic-self-learning
微电子和集成电路自学指南
tharunchitipolu/Dadda-Multiplier-using-CSA
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
hibagus/64pointFFTProcessor
Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
mihir8181/VLSI-Design-Digital-System
This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details
zhangmozhe/microshift_compression
Microshift Compression: An Efficient Image Compression Algorithm for Hardware
maazm007/vsdsquadron-mini-internship
VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.
srohit0/mida
Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"
VardhanSuroshi/VLSI-ASIC-Design-Flow
This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
synogate/gatery
Gatery, a library for circuit design.
shandilyaguy247/ECE3002_VLSI_System_Design
Contains all the necessary lab tasks (Cadence Virtuoso) for ECE3002 VLSI System Design (VIT).
zwhexplorer/Spiking-Neural-Network-Accelerator-EE552-project
Spiking Neural Network Accelerator
lip6/alliance-check-toolkit
Tutorial, examples and regression tests for Coriolis & Alliance (LIP6)
paripath/cdf
Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format
efabless/ravenna
32-bit RISC-V microcontroller
maazm007/100Daysof_RTL
The Repository contains the code of various Digital Circuits
0xharry/RTL2GDS
A tool to compile your RTL files into GDSII layouts.
Electro-SPY/Phase-Locked-Loop
We are designing a CP-PLL. The following link provides resources about PLL design.
karthik-r-rao/VLSI_Physical_Design_Tool
A simple tool to demonstrate the physical design steps of VLSI Design Flow.
SACHINUR17/VLSI-Design-Verification-Projects
This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects
krutideepanpanda/RISC-V-based-micro-controller-using-OpenLane
This is part of EC383 - Mini Project in VLSI Design.
mnmhdanas/UART-protocol
UART - RTL Design and Verification
ChrisShakkour/RV32I-MAF-project
Designinig a Pipeline in-order 5 stage RISC-V core RV32I-MAF
rohankalbag/vlsi-design
VLSI Design - Autumn Semester 2022 - Indian Institute of Technology Bombay
Sooryakiran/Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project
Implementation of Vector Reduce Min and Vector Negation ASIC Hardware, plus a toy CPU, memory and custom ISA for demo. Can be compiled to Verilog. Demos include fib series computations using custom ISA (and custom assembly) and some vector programs.
Kethasriramya2912/Verilog-RTL-Coding
"Mastering RTL-Coding : From Fundamentals to Advanced Programming Techniques using Verilog,System Verilog and UVM"
neeraj1397/A-Primer-For-Physical-Design-Automation
This repository contains python code snippets that implement several algorithms for automating the VLSI Physical Design process. This is based on the learnings from the course - EE5333W (Introduction to Physical Design Automation) at IITM.
Vishakha7501/Sky-130-RTL-Design-and-Synthesis-Workshop-using-Verilog
RTL Design and Synthesis Workshop using Verilog with Sky130 Technology
iamraufu/BRACUCSE460
VLSI Design - Spring 2022
mnmhdanas/Automatic-washing-machine
This project proposes to demonstrate the capabilities and scope of Verilog HDL by implementing the control system of an automatic washing machine. The above mentioned objective by implementing the Control System of an automatic washing using the Finite State Machine model. The washing machine control system generates all the control signals required for the operation of washing machine and is designed using Verilog HDL.
CIE-PESU/CIE_RISCV_Project
RISC-V K-Nearest Neighbors Accelerator for Image Recognition on FPGA
pesadaum/pesadaum
Sobre mim
synogate/gatery_template
Template project for using gatery