harsh-kmr/verilog_experiments

This repository is created for VLSI Experiments in Verilog for Engineering Sem 5 based on the Syllabus of IIIT Trichy. Here you can find the necessary codes, design files, and documentation for the experiments

VLSI Experiments in Verilog for Engineering Sem 5 based on Syllabus of IIIT Trichy

VLSI experiments in accordance with syllabus of IIIT Trichy

Introduction

This repository is created for VLSI Experiments in Verilog for Engineering Sem 5 based on the Syllabus of IIIT Trichy. Here you can find the necessary codes, design files, and documentation for the experiments

List of Experiments

1. Adders and subtractors
2. Mux & Demux
3. Encoders & Decoders
4. Flip-Flops
5. Shift-Registers
6. Working with RAM
7. Comparators, parity generators & ALU
8. Counters
9. Carry look ahead adder
10. Multipliers

Requirements

1. Xilinx ISE Design Suite.
2. Verilog Simulator.

Installation

1. Download and install Xilinx ISE Design Suite from the Xilinx website.
2. Download the Verilog Simulator from any of the Verilog Simulator websites.

Instructions for Use

• Clone the repository to your local machine.
• Open the experiment file you wish to use in the Xilinx ISE Design Suite.
• Simulate and test the code using the Verilog Simulator.

Contributing

Contributions are always welcome!

1. Fork the repository on Github.
2. Clone the repository to your local machine.
3. Make your changes and push them to your fork.
4. Submit a pull request to the main repository.

Conclusion

This repository provides the necessary codes and design files for VLSI Experiments in Verilog for Engineering Sem 5 based on the Syllabus of IIIT Trichy. The experiments cover a wide range of topics and provide a comprehensive understanding of Verilog programming. If you have any questions or suggestions, feel free to contact us. Happy Experimenting!

🚀 About Me

Hi I am Harsh kumar and,

I'm a Machine Learner with ECE background.

🔗 Links