vlsi
There are 253 repositories under vlsi topic.
The-OpenROAD-Project/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
limbo018/DREAMPlace
Deep learning toolkit-enabled VLSI placement
VLSI-EDA/PoC
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
OpenTimer/OpenTimer
A High-performance Timing Analysis Tool for VLSI Systems
DegateCommunity/Degate
A modern and open-source cross-platform software for chips reverse engineering.
nitram2342/degate
Open source software for chip reverse engineering.
arm-university/VLSI-Fundamentals-Education-Kit
Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical implementation of a simplified microprocessor
efabless/openlane2
The next generation of OpenLane, rewritten from scratch with a modular architecture
AUCOHL/DFFRAM
Standard Cell Library based Memory Compiler using FF/Latch cells
antonblanchard/vlsiffra
Create fast and efficient standard cell based adders, multipliers and multiply-adders.
purdue-onchip/gds2Para
GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
asyncvlsi/act
ACT hardware description language and core tools.
phoeniX-Digital-Design/phoeniX
phoeniX RISC-V Processor
danchitnis/EEsim
A browser-based SPICE circuit simulator
cuhk-eda/Xplace
Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization
hsluoyz/Atalanta
Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
NTU-LaDS-II/FAN_ATPG
FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
ahmed-agiza/EDAViewer
EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
luckyrantanplan/nthu-route
VLSI EDA Global Router
varunnagpaal/Digital-Hardware-Modelling
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
OpenTimer/Parser-SPEF
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
ieee-ceda-datc/RDF-2019
DATC RDF
asyncvlsi/AMC
AMC: Asynchronous Memory Compiler
twweeb/VLSI-Physical-Design-Automation
Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
AngeloJacobo/OpenLANE-Sky130-Physical-Design-Workshop
Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
tharunchitipolu/Dadda-Multiplier-using-CSA
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
ahirsharan/32-Bit-Floating-Point-Adder
Verilog Implementation of 32-bit Floating Point Adder
imsanjoykb/Electrical-And-Electronic-Engineering-Course-Materials
Electrical And Electronic Engineering Course Materials
leviathanch/qtflow
A Qt5 based free VLSI development tool
AUCOHL/OGRE
Global Router Built for ICCAD Contest 2019
mediaic/Crash_Course_for_New_Members
Deep Learning & VLSI Crash Course for New Members
andrsmllr/magic_vlsi_examples
Some simple examples for the Magic VLSI physical chip layout tool.
jinwookjungs/lefdef_util
A LEF/DEF Utility.
srohit0/mida
Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"
ucdrstdenis/cdsAsync
cdsAsync: An Asynchronous VLSI Toolset & Schematic Library
Akashtailor-exe/30-days-of-verilog
30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!