/Verilog-projects

ALU (Arithmetic and Logic Unit), Ripple carry adder, Half adder and full adder are designed using all 3 styles (structural, behavioral, dataflow) and tested by generating stimulus using testbench

Primary LanguageVerilog

VLSI-project

Required softwares: ModelSIM - intel FPGA starter edition, Notepad++.

ALU (Arithmetic and Logic Unit), Ripple carry adder, Half adder and full adder designed using all 3 styles (structural, behavioral, dataflow) and tested by generating stimulus using testbench