PyHDI/Pyverilog

Issues

• dataflow analysis error

  #109 opened 3 years ago by cemery123
  6

• Specify statements

  #115 opened 3 years ago by lilasrahis
  1

• Bug: ports mentioned in verilog file are taken as declaration.

  #135 opened 9 months ago by rahultanwar10
  0

• Request: Add generated API documentation for this library

  #134 opened a year ago by parker-research
  0

• Feature Request: Add strong typing to this library

  #133 opened a year ago by parker-research
  0

• isWireArray(termtype) is missing in /utils/signaltype.py

  #90 opened 5 years ago by teaalltr
  3

• TypeError: generate() got an unexpected keyword argument 'reorder' line 100 in Pyverilog/examples/example_graphgen.py

  #131 opened a year ago by zhangshuaiAA9
  2

• TypeError: generate() got an unexpected keyword argument 'reorder'

  #117 opened 3 years ago by Sanjaya97
  3

• Parse Error: Cannot parse a function

  #124 opened 2 years ago by KatCe
  1

• ANSI Style localparam causes parsing error

  #129 opened a year ago by mclark-iontra
  0

• AST node

  #122 opened 2 years ago by lijiale6224
  1

• About control flow analysis

  #105 opened 3 years ago by earphonebreaker
  0

• Codegen arrays

  #128 opened 2 years ago by CapucinedeBoissac
  0

• Unsized numbers without base solution

  #127 opened 2 years ago by YSJL
  0

• Unsized numbers without base not supported

  #116 opened 3 years ago by Louis-DR
  2

• parser error

  #126 opened 2 years ago by 1353369570
  0

• Attribute error in parser

  #125 opened 2 years ago by KatCe
  0

• Preprocessing Issue when included file is in different directory

  #123 opened 2 years ago by YSJL
  1

• Can not support "generate case" statement

  #121 opened 2 years ago by TonyLiaoZP
  0

• unsufficient parse for large scale verilog design

  #118 opened 3 years ago by ZhaoYunfei123
  0

• Can it work on hierarchy of design?

  #81 opened 5 years ago by jadonrahul
  2

• Error running example_graphgen.py

  #92 opened 4 years ago by zhileiren
  1

• Parsing Issues

  #114 opened 3 years ago by kwmartin
  1

• ParseError for User Defined Primitives

  #113 opened 3 years ago by TheMatt2
  1

• Parser Error for resettable D Flip-Flop

  #112 opened 3 years ago by kwmartin
  1

• Parse Error for Inverter Gate

  #111 opened 3 years ago by kwmartin
  0

• function in module can not be parse, and get error

  #77 opened 5 years ago by asky26
  13

• Parsing Error for integer memories

  #110 opened 3 years ago by kwmartin
  0

• TypeError: generate() got an unexpected keyword argument 'reorder'

  #97 opened 4 years ago by venkateshknpl
  2

• Extracting design information via API

  #108 opened 3 years ago by svenka3
  0

• How to setup and install pyverilog inside py virtual environment?

  #106 opened 3 years ago by usman1515
  1

• windows error -run example_parser.py

  #104 opened 3 years ago by TobyLQ
  1

• A bug when parsing nesting ifStatement

  #102 opened 4 years ago by Yang-Qirui
  0

• Functions with port lists can't be parsed

  #100 opened 4 years ago by noloerino
  0

• error

  #96 opened 4 years ago by 61cc
  0

• Modify AST generated by PyVerilog

  #95 opened 4 years ago by sazadur
  0

• How to append new assign to a module from verilog code?

  #94 opened 4 years ago by zilongwang123
  0

• how

  #93 opened 4 years ago by zilongwang123
  0

• gate level netlist to rtl

  #91 opened 5 years ago by very3b
  0

• ast.IntConst creates collisions on dicts

  #84 opened 5 years ago by Lucaz97
  2

• OSError: Format: "dot" not recognized. Use one of:

  #89 opened 5 years ago by faruqui13
  0

• SVA assert / assume/ cover property support

  #87 opened 5 years ago by dyadav7
  1

• The verilog parser doesn't support the dot operator in the module header

  #80 opened 5 years ago by Manarabdelaty
  1

• Delays incorrectly printed on output to verilog

  #82 opened 5 years ago by jandreasen3
  1

• question regarding implementation

  #86 opened 5 years ago by nancychang42
  1

• Not able to run

  #85 opened 5 years ago by KaranThakur1998
  0

• vparser/parser.py mkdir arguement error

  #83 opened 5 years ago by GrantBrown1994
  1

• Assignment with strength does not compile

  #76 opened 5 years ago by vperrin59
  0

• Supporting function calls in parameter/localparam value definitions by dataflow.signalvisitor

  #79 opened 5 years ago by shtaxxx
  0

• Module Initiation Syntax

  #78 opened 5 years ago by HamzaShabbir517
  0