parker-research
Electrical and computer engineering researcher at the University of Calgary
University of CalgaryCalgary, AB, Canada
Pinned Repositories
awesome-braille
A survey of mostly-open source braille displays and technologies
ChatDev
Create Customized Software using Natural Language Idea (through LLM-powered Multi-Agent Collaboration)
circt
Circuit IR Compilers and Tools
csaw-2024-entry-docs
Documentation for my entry in the CSAW 2024 competition
Easy_Pokedex
Easy Pokédex is a convenient tool that allows you to access detailed information about Pokémon without having to capture them.
fish-shell
The user-friendly command line shell.
libcsp-gomspace
Cubesat Space Protocol - A small network-layer delivery protocol designed for Cubesats
LLM-Hardware-Experiments
Hardware design (EDA) experiment utilizing Large Language Models to design secure hardware
pass-at-k
A minimalistic Python library to evaluate the pass-at-k metric
picorv32-csaw-2024
PicoRV32 - A Size-Optimized RISC-V CPU
parker-research's Repositories
parker-research/awesome-braille
A survey of mostly-open source braille displays and technologies
parker-research/ChatDev
Create Customized Software using Natural Language Idea (through LLM-powered Multi-Agent Collaboration)
parker-research/circt
Circuit IR Compilers and Tools
parker-research/csaw-2024-entry-docs
Documentation for my entry in the CSAW 2024 competition
parker-research/Easy_Pokedex
Easy Pokédex is a convenient tool that allows you to access detailed information about Pokémon without having to capture them.
parker-research/fish-shell
The user-friendly command line shell.
parker-research/libcsp-gomspace
Cubesat Space Protocol - A small network-layer delivery protocol designed for Cubesats
parker-research/LLM-Hardware-Experiments
Hardware design (EDA) experiment utilizing Large Language Models to design secure hardware
parker-research/pass-at-k
A minimalistic Python library to evaluate the pass-at-k metric
parker-research/picorv32-csaw-2024
PicoRV32 - A Size-Optimized RISC-V CPU
parker-research/rust-hdl
A framework for writing FPGA firmware using the Rust Programming Language
parker-research/verilog-eval
Verilog evaluation benchmark for large language model
parker-research/RISC-V-Processor-csaw-2024
Verilog implementation of multi-stage 32-bit RISC-V processor
parker-research/ShinyVerilogIFT
RTL-Level Information Flow Tracking for Verilog code
parker-research/ultraembedded-riscv-csaw-2024
RISC-V CPU Core (RV32IM)