PyHDI/Pyverilog

Extracting design information via API

svenka3 opened this issue · 0 comments

svenka3 commented

I like the examples provided such as parser, dataflow etc. Thanks a lot for doing this great work!

Say I want to use PyVerilog to query design information such as:

  1. ports
  2. All net names
  3. All escaped identifiers etc.

How do I approach? I looked at SignalAnalyze, visit_ports etc. but not clear on what the node argument and how to pass it. Any inputs please