Parse Error for Inverter Gate

[kwmartin]

The following parses fine:

`timescale 1ps/10fs
module dg_inv (in,out,vdd,vss);
input in,vdd,vss;
output out;
    not #(20) inv (out,in);
endmodule

Also, the following parses fine:

`timescale 1ps/10fs
module dg_inv (in,out,vdd,vss);
input in,vdd,vss;
output out;
    not (out,in);
endmodule

However, the following gives a parsing error:

`timescale 1ps/10fs
module dg_inv (in,out,vdd,vss);
input in,vdd,vss;
output out;
    not #(20) (out,in);
endmodule

From Syntax table 7-1 for gate instantiation, it appears to me that name_of_gate_instance is optional and that the last case should parse as being correct?