The verilog parser doesn't support the dot operator in the module header
Manarabdelaty opened this issue · 1 comments
Manarabdelaty commented
In the attached example, the parser can't process the .mem({ \mem[0][0] , \mem[0][1] , \mem[1][0] , \mem[1][1] })
in the module header.
Iverilog compiles the verilog file without flagging any syntax errors, so I assume it is valid verilog.
shtaxxx commented
Sorry for the late response.
I would like to fix this point in the next version with the SystemVerilog support.