Supporting explicit Block RAM generation
iitaku opened this issue · 1 comments
iitaku commented
I'm requesting to make it possible to treat Block RAM explicitly in veriloggen. I want to create line-buffer which is composed of register and BRAM.
shtaxxx commented
veriloggen 1.7.0 supports two intermediate buffers (RingBuffer and Scracthpad) in Stream mode. RingBuffer is a BRAM-based extension for delayed values, such like var.prev(delay_size). Though the original prev() consumes Regs to store the delayed values, RingBuffer utilizes BRAM for longer delay intervals. Scratchpad is another extension that supports explicit addressing of read/write for delayed values.
Please try it! Thanks for your comment.