calyxir/calyx

Issues

• Tracker: binary heaps

  #2067 opened a month ago by anshumanmohan
  3

• Allowing for nested `ref` cell instantiation

  #2079 opened a month ago by nathanielnrn
  4

• [Cider 2] Connect to fud2 and the existing test suites

  #2044 opened 22 days ago by EclecticGriffin
  0

• Allowing `invokes` to pass in subtypes to `ref` cells

  #2015 opened 25 days ago by nathanielnrn
  1

• Combinational memories in `gen_exp` and `gen_ntt_pipeline`

  #2062 opened a month ago by anshumanmohan
  1

• Floating-point constants

  #2061 opened a month ago by rachitnigam
  0

• Docs: CIDR configuration instructions

  #2050 opened a month ago by anshumanmohan
  4

• Toplevel `ref` cells are not kept after `compile_invoke` pass

  #1993 opened a month ago by nathanielnrn
  1

• Separate Out FSM in IR when during TDCC and `compile-static`

  #2020 opened 3 months ago by calebmkim
  21

• [Profiling] Tracker Issue for Profiling first steps

  #2014 opened 3 months ago by ayakayorihiro
  4

• [fud2] Mode that is friendly to parallel builds, with a unique per-run workdir name

  #2066 opened a month ago by sampsyo
  5

• Compilation bug: overeager cell sharing

  #2057 opened a month ago by anshumanmohan
  9

• Builder: Support for Combinational Components

  #2047 opened a month ago by anshumanmohan
  1

• `fud`: remove dependency on `calyx-py`

  #2046 opened 2 months ago by anshumanmohan
  0

• Add `CONTRIBUTING.md`

  #1981 opened 4 months ago by rachitnigam
  3

• New metadata format

  #1979 opened 2 months ago by eliascxstro
  2

• [Cider 2] Handle memory input/output

  #1968 opened 2 months ago by EclecticGriffin
  4

• Queues: Rethinking our PIFO

  #1999 opened 3 months ago by anshumanmohan
  1

• `@data` default assignment optimization does not work on external memories

  #2012 opened 2 months ago by andrewb1999
  3

• [fud2] Hypergraph

  #1958 opened 4 months ago by sampsyo
  2

• Use External Libraries To Generate A Single Verilog File

  #1985 opened 4 months ago by jiahanxie353
  0

• Nondeterminism in wire initialization when using `ref` cells.

  #2016 opened 2 months ago by nathanielnrn
  0

• `cell-share` Needs a Timing-Based Heuristic or Cost Model

  #2021 opened 3 months ago by andrewb1999
  1

• eDSL: reserved names, nonexistent ports

  #2017 opened 3 months ago by anshumanmohan
  2

• Toplevel `ref` cells interfere with static promotion

  #1956 opened 4 months ago by ayakayorihiro
  4

• Do a Better Job At Removing Default Zero Assignments

  #2011 opened 3 months ago by andrewb1999
  0

• Change `yxi` backend to look for `ref` memories in addition to `@external` memories

  #1932 opened 5 months ago by nathanielnrn
  1

• Eventually remove `tests/xilinx/cocotb` directory

  #1998 opened 3 months ago by nathanielnrn
  0

• Parse error for large constants

  #1989 opened 3 months ago by Mark1626
  2

• Report multiple errors

  #1924 opened 5 months ago by sgpthomas
  5

• Tests are being duplicated

  #1984 opened 4 months ago by rachitnigam
  1

• [Cider 2.0] Groups taking an extra cycle to exit

  #1917 opened 4 months ago by EclecticGriffin
  4

• Support for arbitrary widths greater than 64

  #1969 opened 4 months ago by matth2k
  4

• Default nettype of inline verilog primitives is unset

  #1966 opened 4 months ago by matth2k
  3

• `clk` signal not respecting cycle length

  #1961 opened 4 months ago by paili0628
  4

• Components that do a single read/write to a `seq_mem` generate circular combinational logic

  #1963 opened 4 months ago by nathanielnrn
  2

• Performance Dashboard Planning

  #1960 opened 4 months ago by parthsarkar17
  2

• `seq-mem` outputs `x`s when not explicitly assigning to `write_en`

  #1955 opened 4 months ago by nathanielnrn
  4

• Cannot publish `calyx-lsp`

  #1947 opened 4 months ago by rachitnigam
  4

• Change well-formedness check to allow for toplevel `ref` memories

  #1933 opened 4 months ago by nathanielnrn
  2

• Create an `external-to-ref` pass

  #1918 opened 4 months ago by nathanielnrn
  3

• Calyx LSP Tracker / Wishlist

  #1951 opened 4 months ago by sgpthomas
  0

• Build script fails to update primitives folder

  #1940 opened 4 months ago by rachitnigam
  0

• Reorganize top-level folder

  #1941 opened 4 months ago by rachitnigam
  0

• Calyx website revamp wishlist

  #1926 opened 5 months ago by rachitnigam
  4

• Make `calyx-py` AXI wrapper `cocotb` testbench accept `yxi` interfaces and dynamic input data

  #1938 opened 4 months ago by nathanielnrn
  0

• Default assignments for non-`@data` ports

  #1919 opened 5 months ago by rachitnigam
  5

• Update Rust version in CI

  #1923 opened 5 months ago by sgpthomas
  2

• fud dependency on calyx-py

  #1916 opened 5 months ago by eys29
  3

• Parameter-dependent attribute values

  #1915 opened 5 months ago by rachitnigam
  0