This repository contains the source code of a timestamping mechanism developed by SRS for both Zynq MPSoC and RFSoC devices, including RTL and C code, project generation scripts and extensive documentation. The solution is targeting a typical SDR implementation in which the transmission and reception of I/Q samples is triggered by a call to a software function. Two different approaches are supported towards this end:
- Use the Zynq-based board as an SDR front-end: that is, the Zynq-board directly interfaces the RF and implements the timestamping solution, whereas the SDR application runs in a host that is connected to it via Ethernet/USB. For this use case, the following platforms are explicitly supported:
- Use the Zynq-based board as a fully embedded SDR solution: that is, the Zynq-board directly interfaces the RF (or has it embedded it in the SoC; e.g., RFSoC), implements the timestamping solution (in the FPGA, where you could also accelerate other DSP functions) and also hosts the SDR application (in the embedded ARM). For this use case, the following platforms are explicitly supported:
- Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit
- Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit
For the sake of convenience this repository includes the code which is specific to the Zynq timestamping solution and uses submodules for the related code that is external to it, including the srsRAN 4G/5G software radio suite and Analog Devices HDL library. The latter is used because the timestamping solution is targeting AD936x-based front-ends for MPSoC architectures.
The full details of the Zynq timestamping solution can be found in the documentation page. Additionally, dedicated application notes are covering all required steps from build to test:
- End-to-end 4G testing with the AntSDR.
- Tx-Rx testing with the ADALM-PLUTO.
- Petalinux build, software cross-compilation and Tx-Rx testing with ZCU102/ZCU111 boards.
We recommend you to go through the application notes, as the detailed steps can be (often easily) modified/reused to target different boards and/or SDR applications.
Please, use the Zynq timestamping Discussions space for discussion and community support. Make sure to read the overview and to follow the guidelines when opening a new discussion point.
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The solution has been developed, validated and tested using:
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Vivado 2019.2
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SRS Python Tools:
cd python_tools sudo pip3 install -U pip pip3 install . -
[optional] For documentation:
npm install teroshdl
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To clone the repository and the utilized submodules:
git clone --recursive
Pre-built images for all supported boards can be found attached as an asset to the released code.