Pinned Repositories
AES-Processor
AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emulation Competition 2016.
AMBA_APB_SRAM
AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).
h265-encoder-rtl
Learn-Algorithms
算法学习笔记
SystemOnFPGA
SOC system using verilog on FPGA devices.
USTCRVSoC
一个用 SystemVerilog 编写的，RISC-V 架构的 CPU + SoC
uvm_auto
uvm auto generator
uvm_candy_lover
:candy:UVM candy lover testbench which uses YASA as simulation script
uvmprimer
Contains the code examples from The UVM Primer Book sorted by chapters.
YASA-1
:snail:Yet Another Simulation Architecture
courageheart's Repositories
courageheart/h265-encoder-rtl
courageheart/AMY_MCU
A MCU implementation based PODES-M0O
courageheart/awesome-dv
Awesome ASIC design verification
courageheart/cocoon
An infrastructure for integrated EDA
courageheart/core-v-mcu-uvm
CORE-V MCU UVM Environment and Test Bench
courageheart/cpplinks
A categorized list of C++ resources.
courageheart/e200_opensource
The Ultra-Low Power RISC Core
courageheart/e203_hbirdv2
The Ultra-Low Power RISC-V Core
courageheart/eFPGA---RTL-to-GDS-with-SKY130
This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
courageheart/fpu
synthesiseable ieee 754 floating point library in verilog
courageheart/fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
courageheart/HDLGen
courageheart/ic_flow_platform
IFP (ic flow platform) is an integrated circuit design flow platform, mainly used for IC process specification management and data flow contral.
courageheart/NandFlashController
AXI Interface Nand Flash Controller (Sync mode)
courageheart/NutShell
RISC-V SoC designed by students in UCAS
courageheart/oh
Silicon proven Verilog library for IC and FPGA designers
courageheart/Open-USB2.0-Device-Controller
USB2.0 Device Controller IP Core
courageheart/opentitan
OpenTitan: Open source silicon root of trust
courageheart/openwifi
open-source IEEE802.11/Wi-Fi baseband chip/FPGA design
courageheart/PLL_Sky130
VSD-IAT PLL IC DESIGN WORKSHOP (31st July, 2021 - 1st August, 2021)
courageheart/Practical-UVM-IEEE-Edition
This is the repository for the IEEE version of the book
courageheart/python-api-tesing
python中文库-python人工智能大数据自动化接口测试开发。 书籍下载及python库汇总https://china-testing.github.io/
courageheart/Python4RTLVerification
courageheart/raven-picorv32
Silicon-validated SoC implementation of the PicoSoc/PicoRV32
courageheart/riscv-cores-list
RISC-V Cores, SoC platforms and SoCs
courageheart/sky130-10-bit-SAR-ADC
A 10bit SAR ADC in Sky130
courageheart/SKY130_SAR-ADC
Fully-differential asynchronous non-binary 12-bit SAR-ADC
courageheart/SpinalHDL
SpinalHDL core
courageheart/uvm_testbench_gen
Novel GUI Based UVM Testbench Template Builder
courageheart/wujian100_open
IC design and development should be faster，simpler and more reliable