craigjb

Scottsdale, AZ

Pinned Repositories

DX7-JTAG
Adapter board for access to the Kintex and MachXO2 JTAG ports on a HAPS-DX7
2 3 00
fuse-zynq
Generate Zynq configurations without using the vendor GUI
Language:Python29 6 00
gameslab-smc
Gameslab system management controller firmware
Language:Rust6 4 01
multimidi
M-M-M-MultiMIDI firmware
Language:Rust7 3 00
riscv-blinky
Blinking with Rust on RiscV (VexRiscv) on SpinalHDL on ECP5 using Symbiflow
Language:Scala10 5 11
slabboy
Gameslab HW emulator for a certain handhold gaming system
Language:Scala10 3 03
SpinalCortex
SpinalHDL usage of ARM Cortex-M0 DesignStart core
Language:Scala5 4 01
spinalsby
SpinalHDL interface to SymbiFlow Yosys for running formal verification
Language:Scala2 3 00
VoltaHDL
A hardware description language for PCB design and verification
Language:Python3 6 01

craigjb's Repositories

craigjb/fuse-zynq
Generate Zynq configurations without using the vendor GUI
Language:Python29 6 00
craigjb/riscv-blinky
Blinking with Rust on RiscV (VexRiscv) on SpinalHDL on ECP5 using Symbiflow
Language:Scala10 5 11
craigjb/slabboy
Gameslab HW emulator for a certain handhold gaming system
Language:Scala10 3 03
craigjb/multimidi
M-M-M-MultiMIDI firmware
Language:Rust7 3 00
craigjb/gameslab-smc
Gameslab system management controller firmware
Language:Rust6 4 01
craigjb/SpinalCortex
SpinalHDL usage of ARM Cortex-M0 DesignStart core
Language:Scala5 4 01
craigjb/VoltaHDL
A hardware description language for PCB design and verification
Language:Python3 6 01
craigjb/DX7-JTAG
Adapter board for access to the Kintex and MachXO2 JTAG ports on a HAPS-DX7
2 3 00
craigjb/spinalsby
SpinalHDL interface to SymbiFlow Yosys for running formal verification
Language:Scala2 3 00
craigjb/BFFPGA
RTL to make a Big Fun FPGA board work
Language:Verilog1 3 0
craigjb/cgmathdemo
A quick demo of using cgmath for 3D math in Rust
Language:Rust1 3 00
craigjb/SpinalLiteDram
SpinalHDL wrapper for Litex LiteDRAM
Language:Scala11
craigjb/stm32f7xx-hal
A Rust embedded-hal HAL for all MCUs in the STM32 F7 family
Language:Rust1 2 0
craigjb/corescore
CoreScore
craigjb/elkjson
Simple application to use Eclipse Layout Kernel for JSON input and output
Language:Java3 0
craigjb/fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
Language:Python2 0
craigjb/gameslab-u-boot
U-boot ported to the Gameslab
3 0
craigjb/gslinux
Gameslab fork of Linux kernel
Language:C3 0
craigjb/litedram
Small footprint and configurable DRAM core
Language:Python2 0
craigjb/probe-rs
A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host
Language:Rust
craigjb/rust-training-Aug19
Rust training materials from August 2019: https://craigjb.github.io/rust-training-Aug19
4 61
craigjb/rust-wasm
A simple and spec-compliant WebAssembly interpreter
Language:Rust3 0
craigjb/Slabware
Gateware, firmware, and software for the SoundSlab
Language:Rust
craigjb/spade
Spatial Data Structures for Rust
Language:Rust3 01
craigjb/SpinalHDL
SpinalHDL core
Language:Scala
craigjb/stm32l0x3
Peripheral access crate for the STM32L0X3 family
Language:Rust3 0
craigjb/stm32l0x3_hal
STM32L0x3 hardware abstraction layer crate
Language:Rust3 0
craigjb/stm32l0xx-hal
A hardware abstraction layer (HAL) for the STM32L0 series microcontrollers written in Rust
Language:Rust2 0
craigjb/svd2rust
Generate Rust register maps (`struct`s) from SVD files
Language:Rust3 0
craigjb/VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
Language:Assembly