cucapra/dahlia

Unsolved HLS Problems for Intel Backend

Closed this issue · 2 comments

KarlMobed commented

This is a list of unsolved problems for future Edan (ha ha, that sucker!) to deal with relating to HLS and the new backend for the Intel fpga.

1. Banking in multi-dimensional arrays

 Potential conflict with implementation for banked single array
 Is there any chance the Xilinx HLS code would work?
 (#pragma HLS ARRAY_PARTITION)  It compiled with no problems for me on the Intel machine, but I 
 do not know if it that means it would work as intended.

2. Views

 Literally everything
sampsyo commented

Thanks, @KarlMobed!

To expand on each of these, briefly:

  1. The __attribute__ thingy that the Intel OpenCL compiler uses doesn't seem to be per-bank. Instead, you use a "chunk size" parameter. Maybe we can carefully engineer the chunk size to emulate multi-dimensional banking.
  2. Our C/C++ implementation of views uses pointer arithmetic, which isn't available for OpenCL arrays. 🤷‍♀
rachitnigam commented

Stale issue. @KarlMobed never implemented an MVP for the backend that could be merged with master.