cyygo1998

Pinned Repositories

cyygo1998
Config files for my GitHub profile.
00
riscv
RISC-V CPU Core (RV32IM)
Language:Verilog00
ZFVimIM_openapi
vim百度云输入法 / async db source for ZFVimIM, using thirdparty's openapi
Language:Vim Script00
ZFVimIM_pinyin_base
vim拼音输入法 / pinyin for ZFVimIM
Language:Vim script00

cyygo1998's Repositories

cyygo1998/cyygo1998
Config files for my GitHub profile.
00
cyygo1998/riscv
RISC-V CPU Core (RV32IM)
Language:Verilog00
cyygo1998/ZFVimIM_openapi
vim百度云输入法 / async db source for ZFVimIM, using thirdparty's openapi
Language:Vim Script00
cyygo1998/ZFVimIM_pinyin_base
vim拼音输入法 / pinyin for ZFVimIM
Language:Vim script00