Pinned Repositories
cemu
A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education and research.
llvm-project
The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.
soc-simulator
A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
sockraw-udp
在Linux下使用PF_PACKET的Raw Socket实现从以太网到UDP的封装,并支持IPv4 Fragment,重大18计卓班的计网Project
ucore-loongarch32
将uCore移植到Loongarch 32
vie-to-answer
用于小型多人的线下知识竞赛活动的在线抢答器
wg-bench
WireGuard Benchmark using netns and iperf3
CDIM
CQU Dual Issue Machine
openssl
TLS/SSL and crypto library
linux
Linux kernel source tree
cyyself's Repositories
cyyself/bpi-f3-mkimg
cyyself/xs-workload-build
cyyself/riscv-isa-manual
RISC-V Instruction Set Manual
cyyself/ruapu
Detect CPU features with single-file
cyyself/xs-multicore-sim
cyyself/bpi-linux
linux kernel for pi
cyyself/XiangShan
Open-source high-performance RISC-V processor
cyyself/NEMU
cyyself/openssl
TLS/SSL and crypto library
cyyself/xs-env
XiangShan Frontend Develop Environment
cyyself/openssl-rvv-perf
cyyself/CoupledL2
Open-source non-blocking L2 cache
cyyself/verilator-multiple-top
cyyself/HuanCun
Open-source high-performance non-blocking cache
cyyself/cemu-docs
Documentation for CEMU
cyyself/rvb_test
cyyself/pikvm
Open and inexpensive DIY IP-KVM based on Raspberry Pi
cyyself/milkv.io
cyyself/jit-coherence-test
Understand microarchitecture features of I-D Coherence.
cyyself/ipibench
Benchmark IPI performance on Linux Kernel using on_each_cpu
cyyself/LicheeRV-Nano-Build
LicheeRV-Nano-Build
cyyself/pyorayplug
cyyself/jit-benchmark
cyyself/m1tso-linux
Apple Silicon TSO Enabler for Linux
cyyself/pi-linux
Kernel source tree for Raspberry Pi-provided kernel builds. Issues unrelated to the linux kernel should be posted on the community forum at https://forums.raspberrypi.com/
cyyself/rvv-bench
A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
cyyself/ramulator2
Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
cyyself/SNANDer
SNANDer - Serial Nor/nAND/Eeprom programmeR (based on CH341A)
cyyself/rocket-chip
Rocket Chip Generator
cyyself/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more