Project-CS3051

Computer Architecture
Tasks:
• Implement the multi-cycle processor with the ISA from the HH book.
• Add hardware to support Floating Point multiplication 16bx16b FMUL, and a 8-bit shift register.
• Simulate with an ASM program. Do not forget to modify memory to behave as byte-addressable.
• Implement and test with Basys 3 board. Up to +6 points in E2.

FMULL, LSL and LSR in Basys3

-Compilador custom .py

  • Requires Python 3.6 or higher
  • Only supports the following instructions:
    • ADD
    • SUB
    • AND
    • ORR
    • FMUL
    • LSL
    • LSR
    • LDR
    • STR