Pinned Repositories
algorithms
Arty-A7-100-Pmod-VGA
Arty-A7-35-Pmod-VGA
EasierUVM
DOULOS Easier UVM Code Generator
HPServerPSUHack
HP HSTNS-PL11/PL30/PL42 Server PSU Modification for Vehicle Flashing and Programming
IBridgePy_Cpp_src
NetFPGA-10G-VC709
NetFPGA-10G VC709 project
qspiflash
vesc_tool
The source code for VESC Tool. See vesc-project.com
zpsu_mon
darwinbeing's Repositories
darwinbeing/HPServerPSUHack
HP HSTNS-PL11/PL30/PL42 Server PSU Modification for Vehicle Flashing and Programming
darwinbeing/vesc_tool
The source code for VESC Tool. See vesc-project.com
darwinbeing/zpsu_mon
darwinbeing/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
darwinbeing/bit-preserve
Project for capturing vintage, classic, aka old computer schematics in KiCad.
darwinbeing/bldc
The code for my custom BLDC controller.
darwinbeing/edk2-sdm845
Broken edk2 port for sdm845 xD
darwinbeing/esp
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
darwinbeing/fpga-shells2
darwinbeing/iRocket
darwinbeing/open-nic-shell
darwinbeing/riffa
The RIFFA development repository
darwinbeing/rocket-dsp-utils
Tools for integrating DspTools components into a rocket-chip
darwinbeing/sv2chisel
(System)Verilog to Chisel translator
darwinbeing/verilog-ethernet
Verilog Ethernet components for FPGA implementation
darwinbeing/vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
darwinbeing/XilinxBoardStore
darwinbeing/ariane
Ariane is a 6-stage RISC-V CPU capable of booting Linux
darwinbeing/badger2040
Examples and firmware for Badger 2040 and Badger 2040 W
darwinbeing/CBL-Mariner
Linux OS for Azure 1P services and edge appliances
darwinbeing/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
darwinbeing/chisel-awl
darwinbeing/emacs
backup dot emacs
darwinbeing/fabrics
This repository contains implementations for various bus protocols, fabrics and bridges. All of these are designed using Bluespec System Verilog (BSV)
darwinbeing/freedom2
Source files for SiFive's Freedom platforms
darwinbeing/hwacha
Microarchitecture implementation of the decoupled vector-fetch accelerator
darwinbeing/install-qt-action
Install Qt on your Github Actions workflows with just one simple action
darwinbeing/PB560
darwinbeing/pimoroni-pico
Libraries and examples to support Pimoroni Pico add-ons in C++ and MicroPython.
darwinbeing/tesc