Demonstration on using a Soft Core (VexRiscv) built with LiteX on a Colorlight i5/i9 (ECP5).
- OSS CAD Suite
- LiteX
- remember to setup udev rules
If using WSL2:
python3 -m litex_boards.targets.colorlight_i5 --board i9 --revision 7.2 --cpu-type vexriscv --build --load --ecppack-compress
make -C firmware
litex_term --kernel firmware/firmware.bin /dev/ttyACM0
If you started the terminal too late to see the LiteX BIOS, type reboot
to restart the CPU.