Pinned Repositories
buddy
JETCAS-Model-Counting
Code for finding crossbar designs that perform edge detection, with approximate model counting
linuxbrew-core
🍻🐧 Core formulae for the Homebrew package manager on Linux
LLVM-to-crossbar
Mapping loop-free C programs with integer arithmetic to memristor crossbars
lstools-showcase
Showcase examples for EPFL logic synthesis libraries
Model-counting-crossbar-synthesis
Automated synthesis of memristive crossbar circuits by model checking
ramulator-pim
A fast and flexible simulation infrastructure for exploring general-purpose processing-in-memory (PIM) architectures. Ramulator-PIM combines a widely-used simulator for out-of-order and in-order processors (ZSim) with Ramulator, a DRAM simulator with memory models for DDRx, LPDDRx, GDDRx, WIOx, HBMx, and HMCx. Ramulator is described in the IEEE CAL 2015 paper by Kim et al. at https://people.inf.ethz.ch/omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf Ramulator-PIM is used in the DAC 2019 paper by Singh et al. at https://people.inf.ethz.ch/omutlu/pub/NAPEL-near-memory-computing-performance-prediction-via-ML_dac19.pdf
ROBDD-to-crossbar
Implementation of mapping ROBDDs to memristive crossbar circuits
dchakra336's Repositories
dchakra336/LLVM-to-crossbar
Mapping loop-free C programs with integer arithmetic to memristor crossbars
dchakra336/ROBDD-to-crossbar
Implementation of mapping ROBDDs to memristive crossbar circuits
dchakra336/buddy
dchakra336/JETCAS-Model-Counting
Code for finding crossbar designs that perform edge detection, with approximate model counting
dchakra336/linuxbrew-core
🍻🐧 Core formulae for the Homebrew package manager on Linux
dchakra336/lstools-showcase
Showcase examples for EPFL logic synthesis libraries
dchakra336/Model-counting-crossbar-synthesis
Automated synthesis of memristive crossbar circuits by model checking
dchakra336/ramulator-pim
A fast and flexible simulation infrastructure for exploring general-purpose processing-in-memory (PIM) architectures. Ramulator-PIM combines a widely-used simulator for out-of-order and in-order processors (ZSim) with Ramulator, a DRAM simulator with memory models for DDRx, LPDDRx, GDDRx, WIOx, HBMx, and HMCx. Ramulator is described in the IEEE CAL 2015 paper by Kim et al. at https://people.inf.ethz.ch/omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf Ramulator-PIM is used in the DAC 2019 paper by Singh et al. at https://people.inf.ethz.ch/omutlu/pub/NAPEL-near-memory-computing-performance-prediction-via-ML_dac19.pdf