Open IP in Hardware Description Language.
- supported language: Verilog HDL, VHDL
- reach me at balddevin@outlook.com
| Order | Module Name | Descriptions |
|---|---|---|
| 1 | cordic_log | Calculate natural logarithm using hyperbolic CORDIC algorithm. |
| 2 | nr_fft | Calculate Fast Fourier Transform (FFT) for NR bandwidth. |
| 3 | booth_mul | 64x64 Booth-Wallace multiplier, pipelined to 3 stages*. |
| 4 | srt_div | 64-bits radix2-SRT, radix-4 SRT division*. |
| 5 | uart | Universal asynchronous Receiver Transmitter. |
- : The design documents can be found HERE.
| Order | Scripts Name | Descriptions |
|---|---|---|
| 1 | vsim.pl | Perl scripts for extracting Mentor Modelsim list information. Usage |
| 2 | clean.pl | Perl scripts for cleaning temp files produced by Modelsim, VCS, Verdi, to use, place this file into your root directory of your project, an effective perl interpreter is required. |
| 3 | makefile | Makefile for execute compilation, simulation, invoke Verdi, and make clean. |
| 4 | clean.sh | Shell scripts to clean Modelsim simulation temp files, place this file into your vsim/ directory, clean.pl will detect this file to perform clean. |
Copyright (c) 2023, devindang
The software is licensed under 3-clause BSD License.