dinesh2212

2nd year ECE Bachelors degree at IIIT-Hyderabad

Hyderabad/Chennai

Pinned Repositories

Carry-Look-Ahead-Adder-MAGIC-layout
Layout of a Carry Look-Ahead Adder using MAGIC VLSI along with extracted SPICE file
Language:SourcePawn10
Carry-look-ahead-adder-Verilog
Implementation of a Carry look-ahead adder (CLA) using Verilog
Language:Verilog00
Costas-Loop-Matlab-Simulation
matlab
Language:MATLAB00
hacktoberfest
Hacktoberfest Hyderabad Repo
Language:C00
ILSBB
It's Like Splitwise, But Better
Language:HTML00
NoteMaker-backend
Language:Python00
NoteMaker-frontend
Language:JavaScript00
NoteMaker-Webapp
00
Reading-Temperature-through-NodeMCU
Language:C++00
Stock-Predicting-RNN
Language:Jupyter Notebook00

dinesh2212's Repositories

dinesh2212/Carry-Look-Ahead-Adder-MAGIC-layout
Layout of a Carry Look-Ahead Adder using MAGIC VLSI along with extracted SPICE file
Language:SourcePawn10
dinesh2212/Carry-look-ahead-adder-Verilog
Implementation of a Carry look-ahead adder (CLA) using Verilog
Language:Verilog00
dinesh2212/Costas-Loop-Matlab-Simulation
matlab
Language:MATLAB00
dinesh2212/hacktoberfest
Hacktoberfest Hyderabad Repo
Language:C00
dinesh2212/ILSBB
It's Like Splitwise, But Better
Language:HTML00
dinesh2212/NoteMaker-backend
Language:Python00
dinesh2212/NoteMaker-frontend
Language:JavaScript00
dinesh2212/NoteMaker-Webapp
00
dinesh2212/Reading-Temperature-through-NodeMCU
Language:C++00
dinesh2212/Stock-Predicting-RNN
Language:Jupyter Notebook00
dinesh2212/T-Rex-Game
Language:Python
dinesh2212/y86_processor
A Y86 processor built and simulated on Verilog HDL
Language:Verilog