This repository contains various small FPGA projects targeting the cheap(-ish) dev board, the Arty A7-35t, made by Digilent. The board has a Xilinx Artix-7 series (XC7A35TICSG324-1L) FPGA. More details of the board can be found on Digilent's website here.
The motivation behind this repository is twofold; one, to track my own progress as I delve more into the world of FPGAs and two, when I complete more designs, to hopefully act as a source of possible project ideas to tackle for others that are beginning their journey into FPGAs.
All the designs are written in VHDL and, presently, none of them contain IP blocks (but this may change in future projects). I have also not included any build scripts for now (hopefully will add them in the future), so if you want to load the design you will have to manually start a project within Vivado, select the correct FPGA chip and add all the vhdl and constraints files into the project. The very basic designs have no testbenches, some have simple testbenches which will require manual inspection of the waveforms in a simulator, others have basic self checking testbenches, and more complicated designs have more sophisticated testbenches that read and write from files where the input is generated and the checking of correctness is done from MATLAB/Python scripts.
Below is brief summary of each project listed in order of completion (so roughly difficulty). The most recent is listed first.
An Advanced Encryption Standard (AES) encryption core with a key length of 128 bits. The round operations and the key schedule are fully pipelined/unrolled, so the core can accept new data and/or a new key every clock cycle. When the pipeline is filled, 128 bits of cipher text are produced every clock cycle. It meets timing with a clock constraint of 300Mhz in Vivado, so has a possible throughput of 38.4 Gbit/s.
Still to do:
- Test against vectors provided by NIST
- Write top module to interface with PC
- Write python script to push keys/plain text data through serial port (USB)
A universal asynchronous receiver-transmitter (UART) implementation. The receiver has 16x oversampling and the incoming bit is determined by a majority vote of the three middle samples. A simple loopback between the pc (via the USB) and the FPGA is implemented on the board.
An 8-bit linear-feedback shift register (LFSR). The output of the LFSR is displayed via the green LEDs on the board. LED 1 pulses when the output is '0' and LED 0 pulses when the output is '1'. The LFSR is slowed down to 1Hz via a clk enable so that we can actually see the output on the board. For the testing of the LFSR, the testbench writes the output to a file. A basic Python script is used to launch the simulation and then compare the output values to reference values which are generated from MATLAB.
Inspired by this scene from The Office, I decided to recreate the bouncing DVD logo screensaver from old DVD players. It is displayed on an external monitor using the same VGA controller developed previously. To save on-chip memory and simplify things, a purely white logo is used. This is stored in ROM, the values for which were generated by parsing an image of the DVD logo with a basic python script.
A Video Graphics Array (VGA) controller using the Digilent PmodVGA. Displays a test pattern on the screen.
Every blinking LED pattern that you could think of. Well, not really, but anyway they are:
- Blink: Blink four LEDs at 1HZ with 50% duty cycle.
- Bounce: The light "bounces" from left to right and back on the four green LEDs.
- Pulse: Pulse LEDs using pulse width modulation (PWM)
- Count: Four green LEDs light up in the sequence of a binary counter
Flick a switch, turn on a green LED. Simple as that.