dmrcmelis/Timed_Moore_inVivado
Implement the timed Moore state machine shown in Figure 1 in VHDL. Write a test bench and simulate the behavior of the state machine. Verify the simulation results by your hand analysis.
Implement the timed Moore state machine shown in Figure 1 in VHDL. Write a test bench and simulate the behavior of the state machine. Verify the simulation results by your hand analysis.