dmukherj09

dmukherj09's Stars

• torvalds/linux

  Linux kernel source tree

  Language:C184k54.4k

• HyTruongSon/Neural-Network-MNIST-CPP

  Neural Network implementation in C++ running for MNIST database.

  Language:C++5117

• quepas/Compiler-benchmark-suites

  A list of benchmark suites used in the research related to compilers, program performance, scientific computations etc.

  464

• EntityFX/anybench

  CPU Benchmarks Set

  Language:C7011

• deplinenoise/ig-memtrace

  Memory Tracing Software

  Language:C#43337

• CMU-SAFARI/prim-benchmarks

  PrIM (Processing-In-Memory benchmarks) is the first benchmark suite for a real-world processing-in-memory (PIM) architecture. PrIM is developed to evaluate, analyze, and characterize the first publicly-available real-world PIM architecture, the UPMEM PIM architecture. Described by Gómez-Luna et al. (https://arxiv.org/abs/2105.03814).

  Language:C14249

• qcjiang/DAMOV

  DAMOV is a benchmark suite and a methodical framework targeting the study of data movement bottlenecks in modern applications. It is intended to study new architectures, such as near-data processing. Described by Oliveira et al. (preliminary version at https://arxiv.org/pdf/2105.03725.pdf)

  Language:C++1

• parthpower/DCC_Basic

  Typical project for Synopsys DC Compiler

  Language:Tcl52

• vim-scripts/pt.vim.gz

  Syntax file for Synopsys PrimeTime tcl

  Language:VimL81

• vlsiencyclopedia/VLSI-Interview-Codes

  1

• UndefeatedSunny/VLSI-Interview-Questions

  Digital Design verilog tricky problems having industry standards

  Language:Verilog221

• vlsiexcellence/Low-Power-VLSI-Design-LPVLSI

  Low Power VLSI Design Concepts & Interview Questions for Top Semiconductor MNCs

  4

• drom/awesome-hdl

  Hardware Description Languages

  97796

• abhowmick22/Simulator

  This is a simulator of a cache + memory hierarchy. It has a trace-driven input interface. The trace files are not included in the project.

  Language:Objective-C31

• nykez/memory-simulator

  A memory hierarchy simulator written in C++

  Language:C++41

• ultraembedded/biriscv

  32-bit Superscalar RISC-V CPU

  Language:Verilog882150

• tanayasija/SST-CacheSim

  Language:C++21

• blucia0a/MultiCacheSim

  A Coherent Multiprocessor Cache Simulator Based on the SuperESCalar Cache Model

  Language:C++2516

• michael-ross-scott/Cache-Simulator

  Simple cache simulator built using Java.

  Language:Java3

• BenniG123/Cachemandu

  A simple, modern looking Cache simulator.

  Language:C#4

• aniketp/multi-level-cache-simulator

  A 3-level cache simulator for SPEC traces with various inclusion and block replacement policies

  Language:C++61

• cache-sim/cache-sim

  cache simulator

  Language:C++810

• seifhelal/Cache-Simulator

  A cache simulator, using the C++ language, to simulate a direct-mapped, fully associative and set-associative cache. It has a set of memory reference generators to generate different sequences of references.

  Language:C++1810

• snie2012/computer-architecture-projects

  Computer architecture related projects

  Language:C++8

• aclements/mtrace

  Memory access tracing QEMU

  Language:C9420