/riscv-cpu-chisel3

Primary LanguageScala

RISCV64 CPU

We choose chisel3 to implement RISCV64 5-stage Pipeline CPU desgined using chisel3.Now it's just a framework.The memory is simluated by cpp code to make tesing easily.

Feature

  • Pipeline
  • Data Hazard

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Getting Started

First, install mill by referring to the documentation here. Then, install verilator by referring to the documentation here. To watch vcd files,gtkwave is nedded.

To run all tests in this design (recommended for test-driven development):

make test

To generate Verilog:

make verilog

DataPath

Datapath