/RegisterFileVHDL

Circuit design of a 16bit register file containing 8 registers written in VHDL.

Primary LanguageVHDLMIT LicenseMIT

RegisterFileVHDL

Circuit design of a 16bit register file containing 8 registers written in VHDL. Operations available include register transfers and loading registers with 16 bit values.

Also contains testbenches for each respective component.

Components

  • Register File
  • Register(16bit)
  • Decoder(3to8)
  • Multiplexer(8to1)
  • Multiplexer(2to1)

Circuit Schematic (Adjusted to 8 x 16bit Registers):
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