doonny
Prof. at The Heterogeneous Computing Lab of Beijing Jiaotong University
Beijing Jiaotong UniversityBeijing, China
Pinned Repositories
alexnet-forwardpath
AlexNet
AlteraOpenCLPCIDriver
Updates to the OpenCL PCI driver used in the DE5Net Board
basic_knowledge
Things to learn for new students in the Lab for AI chips and systems of BJTU .
c5soc_opencl
DE1SOC DE10-NANO DE10-Standard OpenCL hardware that support VGA and desktop. And Some applications such as usb camera YUYV to RGB , Sobel and so on.
Embedded-Neural-Network
collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning
PipeCNN
An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
Vitis-In-Depth-Tutorial
Vitis-Tutorials
Vitis_Accel_Examples
Vitis_Accel_Examples
Vitis_Embedded_Platform_Source
doonny's Repositories
doonny/PipeCNN
An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
doonny/basic_knowledge
Things to learn for new students in the Lab for AI chips and systems of BJTU .
doonny/Embedded-Neural-Network
collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning
doonny/alexnet-forwardpath
AlexNet
doonny/AlteraOpenCLPCIDriver
Updates to the OpenCL PCI driver used in the DE5Net Board
doonny/c5soc_opencl
DE1SOC DE10-NANO DE10-Standard OpenCL hardware that support VGA and desktop. And Some applications such as usb camera YUYV to RGB , Sobel and so on.
doonny/Vitis-In-Depth-Tutorial
doonny/Vitis-Tutorials
doonny/Vitis_Accel_Examples
Vitis_Accel_Examples
doonny/Vitis_Embedded_Platform_Source
doonny/ImageNet_Utils
:arrow_double_down: Utils to help download images by id, crop bounding box, label images, etc.
doonny/oh
An Open Hardware Verilog library for FPGAs and ASICs
doonny/tinker
Tinker: Generating Custom Memory Architectures for Altera’s OpenCL Compiler
doonny/XFER_FPGA
doonny/xilinx_axidma
A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.