dpiegdon/verilog-buildingblocks

Issues

• building for ecp5

  #6 opened 2 years ago by Oscilllator
  3

• bit_ready clock synchronization

  #4 opened 4 years ago by DurandA
  13

• how can I use the TRELLIS_SLICE

  #5 opened 4 years ago by TonyWUD
  4

• Reset signal in LSFR

  #3 opened 5 years ago by DurandA
  6

• Ring oscillator on ECP5

  #2 opened 5 years ago by DurandA
  1