Pinned Repositories
bch_verilog
Verilog based BCH encoder/decoder
catapult-v3-smartnic-re
Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)
Chirp-Signal-Compression-Simulator-CSCS-Matlab-App
CSCS (Chirp Signal Compression Simulator) is a Matlab application for easily simulate the single/multi-target linear frequency modulation (chirp) signal compression
CIC-filter
Cascaded Integrator Comb(CIC) filter implemented in C++
FPGA-Adaptive-Beamforming-and-Radar-Examples
This repository contains FPGA/HDL demonstrations several beamforming and radar designs. Simulink models and MATLAB reference code are provided to showcase high-level simulation and HDL designs of various radar and array processing algorithms.
openofdm
Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
PySAR
InSAR (Interferometric Synthetic Aperture Radar) tim-series analysis in python
radar_matlab
Matlab files for radar detection and phase noise
srsLTE
Open source SDR LTE software suite
wradlib
weather radar data processing - python package
dreamchenhao's Repositories
dreamchenhao/DSView
An open source multi-function instrument for everyone
dreamchenhao/LQFramKit
使用Qt封装的一些控件,以便后期项目中直接使用。这些控件有些是来自于网络有些属于个人封装,代码中都有出处
dreamchenhao/PySAR
InSAR (Interferometric Synthetic Aperture Radar) tim-series analysis in python
dreamchenhao/radar_matlab
Matlab files for radar detection and phase noise
dreamchenhao/srsLTE
Open source SDR LTE software suite
dreamchenhao/wradlib
weather radar data processing - python package
dreamchenhao/CIC-filter
Cascaded Integrator Comb(CIC) filter implemented in C++
dreamchenhao/corundum
Open source FPGA NIC 网络控制器
dreamchenhao/DSPFilters
A Collection of Useful C++ Classes for Digital Signal Processing
dreamchenhao/fpga_design
这是我所开发的两个项目,包括ov5640-ddr3-usb2.0高速图像采集系统以及NOIP1SN1300A-ddr3-sdhc高速地表图像采集及存储系统
dreamchenhao/hdl
HDL libraries and projects
dreamchenhao/inspectrum
Offline radio signal analyser
dreamchenhao/JQTools
基于Qt开发的小工具包
dreamchenhao/libevent-book
Nick's libevent manual
dreamchenhao/net2axis
Verilog network module. Models network traffic from pcap to AXI-Stream
dreamchenhao/notes-linear-algebra
线性代数笔记
dreamchenhao/PYNQ
Python Productivity for ZYNQ
dreamchenhao/PyRadar
CINRAD basic data read and process. Draw PPI, RHI, CAPPI, volume rendering and several 3D model of basic data.
dreamchenhao/QmlBook-In-Chinese
QML Book In Chinese
dreamchenhao/qtcsv
Library for reading and writing csv-files in Qt.
dreamchenhao/Radar_signal_processing_homework
dreamchenhao/scopy
A software oscilloscope and signal analysis toolset
dreamchenhao/SRAI_HW_ACCEL_WINDOWS10_PCIe
PCIe based accelerator for VCU1525 with xDMA based on Windows10 and Windows Server 2016 development environment
dreamchenhao/TransceiverToolbox
MATLAB toolbox for ADI transceiver products
dreamchenhao/verilog
Repository for basic (and not so basic) Verilog blocks with high re-use potential
dreamchenhao/verilog-ethernet
Verilog Ethernet components
dreamchenhao/verilog-lfsr
Fully parametrizable combinatorial parallel LFSR/CRC module
dreamchenhao/verilog-pcie
Verilog PCI express components
dreamchenhao/WishboneAXI
Wishbone to AXI bridge (VHDL)
dreamchenhao/xfcp
Extensible FPGA control platform