This tutorial explains the procedure for creating a RTL Kernel using SDAccel Flow.
Steps for creating a RTL Kernel are:
- Design Overiew
- Launching the RTL Kernel Wizard.
- Integrating the DUT with the FIFO Interface.
- Debug and Verification of RTL Kernel.
- Generating XO file and packaging RTL kernel
- SDAccel program on AWS F1
- References
This tutorial uses aes128 crypto core example from the opensource.org
Downlaod the design files from this link
Hirearchy of the Design Files. We will be working on aes128lowarea design.
The DUT is instantiated in the design two times. The first instance takes in data, key and generates a cipher. The second module uses the cypher, key and decrypt the cypher to give back the original message.
A kernel can be implemented in RTL and developed using the Vivado® IDE tool suite. RTL kernels offer potentially higher performance with lower area and power but requires development using RTL coding, tools, and verification methodologies. The tool generates the basic template of AXI Read/write, FIFO Interface for the user, the user has to add custom logic to talk to this interface.
The RTL Kernel Wizard can be launched with two different methods: from the SDx™ Development Environment or from the Vivado® IDE. The SDx Development Environment provides a more seemless experience, but IP management is limited. The Vivado IDE is recommended if multiple kernels are going to be generated and allows for better re-entrant workflows.
- Launch SDx Development Environment(SDX 2017.1).
- Create Project (SDAccel Product Type) with application Project.
- Click Xilinx > Create RTL Kernel....
- Then you will be prompted with the Create RTL Kernel window, click next, click next, click next.
- Global memory is accessed by the kernel through AXI4 master interfaces. Each AXI4 interface operates independently of each other. Each AXI4 interface may be connected to one or more memory controllers to off chip memory such as DDR4. Global memory is primarily used to pass large data sets to and from the kernel from the host. It can also be used to pass data between kernels.
_This current design uses one AXI Master port and one arguments associated with it, once selected click Next_.
- This page gives a summary of the VLNV, software function prototype and hardware control registers created from options selected in the previous pages. The function prototype conveys what a kernel call would like if it was a C function.
After clicking OK in the summary page, flow will be directed to Vivado.
Xilinx has already developed the interface logic for the user. The responsibility of the user is to integrate the DUT with the interface logic.
Once the Vivado opens
- Click the add files option in the source tab and import all aes128lowarea verilog files.
2.1 The repository contains a sdx_kernel_wizard_0_example_vadd.sv which contains custom logic for interfacing with the FIFO.
2.2 Copy this file contents and paste in the sdx_kernel_wizard_0_example_vadd.sv
3.1 The repository contains a testbench file with the name sdx_kernel_wizard_0_exdes_tb_basic.
3.2 Copy the contents of the file and paste it in the file in the source tab(sdx_kernel_wizard_0_exdes_tb_basic).
After doing these steps, the hirearchy structure should look like this.
- RTL kernels should be verified in their own test bench using advanced verification techniques including Verification components, randomization, and protocol checkers. The AXI Verification IP (AXI VIP) is available in the Vivado® IP catalog and can help with verification of AXI interfaces. The Vadd RTL kernel example design contains an AXI VIP based test bench with sample stimulus files.
- The hardware emulation flow should not be used for functional verification because it does not accurately represent the range of possible protocol signalling conditions that real AXI traffic in hardware may incur. Hardware emulation should be used to test the host code software integration or to view the interaction between multiple kernels.
If you expand the simulation sources in the sources tab, you will see the AXI VIP module as sdx_kernel_wizard_0_exdes_tb_basic. Xilinx has provided a basic framework for the testbench. If the user needs to have a more complex testbench it should be changed depending upon specifications(Please refer to the references for working with Xilinx AXI VIP).
NOTE : The mem_rd_addr and mem_wr_addr has to be changed(easy way of finding this is to simulate the design and note down the m00-wr_addr)
Click on the run simulation button in the flow navigator(Change the simualtion time to 1000ms, by default it will be set to 1us). The testbench has a scoreboard, it uses backdoor memory read API calls and verifies it with golden data.
The final step in creating an SDx kernel is to package the generated vivado project into an xo file.
In vivado, click on the Generate RTL Kernel button in the GUI to create the kernel.
This will package the project as an IP, and then package the IP as a kernel xo file. The IP will be available in the directory _v1_0. The xo ile wil be called .xo. Import the kernel xo file into the SDx project to use the kernel in the SDx project.
Go to this link and follow from Step 3 .