train usage of systemc tlm2
- test systemc lib work
- nb_transport
- b_transport
- apb2, send 3 data sequently
- apb3, send 3 data sequently
- dmi
- dbg interface
- add ignorable extension in generic_payload, take AWCACHE or ARCACHE in AXI as example
- create a class quantum_control to implement break quantum feature
my_processor my_peripheral
0 ms|-------------------------------------
| | |
| V V
50 ms|-------------------------------------sc_current_time() = 50ms
| | | ^
| | | |
100 ms| | | | local_quantum_time = 100ms
| | | |
| | V b_transport() V
150 ms|-------|-----============>-----------
| | | break quantum ^
| | | | sc_time(50, SC_MS)
| | V v
200 ms|-------|-----------------------------
| | new quantum size = 50ms
| |
250 ms| V predicted quantum size = 200ms
|
|
V
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add ignorable extension in gp, implement ARM-v7M local monitor, aim to record FSM. the most important 4 element for FSM is state, event, action and transition. reference doc is ARMv7-M Arichitecture Reference Manual PA3-72.
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implement a fifo model, the idea comes from lecture Operating System, this fifo model is like a monitor, ps: signal change frequently case like this, is not suitable for time decoupling, because every time signal change it should call break quantum in order to get the correct value in time.
| Type | OS | FIFO model |
|---|---|---|
| var | in | uint32_t in |
| out | uint32_t out | |
| count | uint32_t count | |
| buffer | arry[0, ..., n-1] | uint32_t buffer[3] |
| condition | notfull | full.read() |
| notempty | not_empty.read() | |
| wait | notfull.wait | full.write(true) |
| notempty.wait | not_empty.write(false) | |
| signal | notfull.signal | full.write(false) |
| notempty.signal | not_empty.write(true) |
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implement a fifo in model, this fifo uses the concept of semaphore, 11_fifo the fifo is a model
-
implement a round-robin arbiter, the core is a increasing pointer.
-
thread reset feature, thread will restart if condition satisified
- reset_signal_is(..,..) only valid at clk.pos() or clk.neg()
- async_reset_signal_is(..,..) valid at any wait
-
self implement tlm model
- inheritence base abstract class sc_interface to implement abstract template class liushuo_interface;
- inheritence liushuo_interface to implement channel model memory;
- implement a sc_module master to involve sc_port to link with liushuo_interface;
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self implement tlm2 b_transport
- using sc_export, increase code readable;
- add register callback function;
-
sc_mutex, only support atomicity of operation, cannot ensure the sequence of operation, in other words cannot relaize the synchronous of operation.
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sync case, different master send data at the same time, how to execute in order and ensure the quantum of operation
-
add single port multiple interface case
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add custom implement sc_signal case
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add tlm2 export implementation, in tlm2 no export, so combine a general target and a internal initiator as a export
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compare between bus and noc, the difference is router logic, noc is in an ip but for bus is in master and slave.
|————————|
| |-bus.valid---------->|————————|
| | | | bus |
| |-bus.data--|-------->| slave0 |
| | | | | |
| |-bus.addr--|--|----->|————————|
| | | | |
| | | | |-->|————————|
| | | | | bus |
| | | |----->| slave1 |
| | | | |
| | |-------->|————————|
| master |
| | |————————|
| | |—————| | NoC |
| | | |---->| slave0 |
| | | | | |
| | | | |————————|
| |-------->| NoC |
| | | | |————————|
| | | | | NoC |
| | | |---->| slave1 |
| | |—————| | |
| | |————————|
|————————|