dzwduan

dzwduan's Stars

• karpathy/LLM101n

  LLM101n: Let's build a Storyteller

  31k2.6k01.7k

• ccfddl/ccf-deadlines

  ⏰ Collaboratively track deadlines of conferences recommended by CCF (Website, Python Cli, Wechat Applet) / If you find it useful, please star this project, thanks~

  Language:Vue6.7k2291459

• swig/swig

  SWIG is a software development tool that connects programs written in C and C++ with a variety of high-level programming languages.

  Language:C++5.9k1961.8k1.2k

• zachjs/sv2v

  SystemVerilog to Verilog conversion

  Language:Haskell5801728256

• google/llvm-propeller

  PROPELLER: Profile Guided Optimizing Large Scale LLVM-based Relinker

  Language:C++385161836

• aitomatic/semikong

  First Open-Source Industry-Specific Model for Semiconductors

  Language:Python2888833

• aappleby/metron

  A C++ to Verilog translation tool with some basic guarantees that your code will work.

  Language:C++1659314

• tenstorrent/riscv-ocelot

  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support

  Language:Scala15310023

• OfekShilon/optview2

  User-oriented fork of LLVM's opt-viewer

  Language:Python13882114

• regymm/quasiSoC

  Linux capable RISC-V SoC designed to be readable and useful.

  Language:C133729

• robfinch/Cores

  Language:C++739424

• GeorgOfenbeck/perfplot

  tools to create performance and roofline plots from measured data

  Language:C++5813213

• kaist-cp/shakeflow

  ShakeFlow: Functional Hardware Description with Latency-Insensitive Interface Combinators (ASPLOS 2023)

  Language:Rust52311

• pydrofoil/pydrofoil

  A fast RISC-V emulator based on the RISC-V Sail model, and an experimental ARM one

  Language:Python447385

• tenstorrent/whisper

  Language:C++34035

• YanWQ-monad/SUSTech_CS202_Project-CPU

  SUSTech CS202 (Computer Organization) Project, with CPU hardware implemented in Chisel(Scala) and software cross-compiled from Rust.

  Language:Scala29100

• jiegec/cpu

  Microarchitecture diagrams of several CPUs

  18302

• mariobadr/statistical-simulation

  Multiple approaches to statistical simulation for computer architects

  Language:C++15205

• jtsiomb/c-ray

  Minimal C raytracer widely used as a CPU benchmark

  Language:C14203

• OpenXiangShan/xfuzz

  Fuzzing General-Purpose Hardware Designs with Software Fuzzers

  Language:Scala14771

• oscc-ip/sdram

  An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different manufacturers and models through parameter configuration.

  Language:Scala14502

• zhutmost/chipmunk

  Enhance CHISEL for Smooth and Comfortable Chip Design

  Language:Scala14302

• RISMicroDevices/CHIron

  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)

  Language:C++12100

• dtcxzyw/static-key

  Header-only C/C++ static keys to avoid the overhead of conditional branches

  Language:C++11300

• jiegec/chisel-memory-lower

  Lower chisel memories to SRAM macros

  Language:Python1120

• TsaiAnson/verif

  Language:Scala11703

• Anon-233/iFu

  Language:Scala52

• CircuitCoder/DRAMsim3-rs

  Rust binding for DRAMsim3

  Language:Rust510

• BUAA-CI-LAB/eula-env

  Language:Shell3000

• ucb-bar/riscv-coremark-pro

  Compiles coremark-pro for riscv64 baremetal

  Language:Makefile3110