/RetiLogiche-Project

Reti Logiche - Final examination - 2019/2020

Primary LanguageVHDL

Reti Logiche - Project

Reti Logiche - Final examination - From the course held at PoliMi during the year 2019/2020
Final score: 30 cum laude

Aim of the examination

Implementing, through VHDL programming language, an hardware component capable of codifying addresses according to the "Working Zone" method, which consists in codifying the chosen addresses on the basis of the Working Zone they belong to.
All the details about the requirements and the implementation can be found into the Documentation file.