/MIPS_R10K_Processor

2-core MIPS R10K OoO Processor with Snooping MSI and Pipeline Bus

Primary LanguageVerilog

EECS470_Final

  • 2-core MIPS R10K OoO Processor with Snooping MSI and Pipeline Bus
  • coreS: 2-core processor for testing multi-core programs
  • master: single core processor

Key Features:

  1. Multicore with coherent write-back data caches
  2. Early branch recovery
  3. Perceptron predictor (based on neural network)
  4. Store-to-load forwarding in LSQ
  5. Load issue out-of-order past pending stores
  6. Multiple outstanding load misses
  7. Store buffer
  8. Next-line prefetching
  9. Write-back data cache
  10. Cache associativity > 1
  11. Victim cache