ei9/cpu

RISC-V core in Verilog, rv32ui, single cycle design.

CPU

Click here for more mini processor i made before.

Passed rv32ui unit tests from riscv-tests repository.

Implements some of the RISC-V RV32I instruction set. Except:

Not implemented instructions

• fence, fence.i
• ecall, ebreak
• csxxx

Reference

Jim's Dev Blog

Free & Open RISC-V Reference card

Thanks to georgeyhere/Toast-RV32i. I learned a lot about how to do riscv-tests from it's Makefile and scripts. I modified the script to make it able to build hex file using riscv64-unknown-elf for rv32i.