ejongengr

ejongengr's Stars

• AppFlowy-IO/AppFlowy

  Bring projects, wikis, and teams together with AI. AppFlowy is an AI collaborative workspace where you achieve more without losing control of your data. The best open source alternative to Notion.

  Language:Dart57.6k3.8k

• opalkelly-opensource/design-resources

  A collection of Opal Kelly provided design resources

  Language:Verilog159

• dayalannair/FMCW_FFT_Radar

  Implementation of the Xilinx FFT IP using a UART packetised data stream

  Language:VHDL71

• minwoo0611/HeLiPR-Pointcloud-Toolbox

  The HeLiPR Pointcloud Toolbox is a sophisticated software suite tailored for processing and analyzing the HeLiPR (Heterogeneous LiDAR Place Recognition) dataset.

  Language:C++311

• DoongLi/awesome-FMCW-LiDAR

  A curated list of FMCW-LiDAR papers and resources.

  193

• WangXuan95/FPGA-USB-Device

  An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。

  Language:Verilog604102

• CircuitSetup/Split-Single-Phase-Energy-Meter

  Split Single-phase Energy Meter

  Language:C++26357

• BBN-Q/VHDL-JESD204b

  JESD204b modules in VHDL

  Language:VHDL2919

• Nitcloud/Digital-IDE

  在vscode上的数字设计开发插件

  Language:Verilog32520

• Xilinx/Vitis-Tutorials

  Vitis In-Depth Tutorials

  Language:C1.2k553

• Significant-Gravitas/AutoGPT

  AutoGPT is the vision of accessible AI for everyone, to use and to build on. Our mission is to provide the tools, so that you can focus on what matters.

  Language:Python168k44.3k

• milovanovic/cfar

  A Constant False Alarm Rate Processor Generator

  Language:Scala71

• farbius/dsp_xilinx_ip

  Some basic DSP algorithms implemented with xilinx IP cores with explanation, Verilog testbenches and modelling in Python

  Language:Verilog2911

• farbius/kb_radar_course

  Language:VHDL65

• pConst/basic_verilog

  Must-have verilog systemverilog modules

  Language:Verilog1.6k379

• ts-manuel/DDS-Function-Generator

  FPGA-Based DIY Function Generator

  Language:C489

• michaelbecker/freertos-addons

  Additions to FreeRTOS

  Language:C454102

• alexforencich/verilog-axis

  Verilog AXI stream components for FPGA implementation

  Language:Python736226

• ship-cse/meta-sevenseg

  Yocto Linux "meta-sevenseg" from my Vivado videos

  Language:C6

• CalPlug/Microsemi_SmartFusion2_TrainingProjects

  Example Projects for the Microsemi SmartFusion 2

  Language:C92

• HDLForBeginners/Examples

  Language:Verilog7525

• ben-marshall/verilog-doc

  A basic documentation generator for Verilog, similar to Doxygen.

  Language:C112

• alkgrove/partlocater

  Find a part on Digi-Key and import parameters into local database

  Language:Python163

• tjschweizer/IC-Inventory

  Python project to work with the Octopart API. Goal is to make a program that allows me to search for IC part numbers, and add them to a local inventory. Full details at learn-cnc.com

  Language:Python72

• theterg/pyoctopart

  A simple Python client frontend to the Octopart public REST API.

  Language:Python1

• guyzmo/pyoctopart

  A simple Python client frontend to the Octopart public REST API.

  Language:Python912

• mymy49/yss

  Language:C5812

• nschloe/perfplot

  :chart_with_upwards_trend: Performance analysis for Python snippets

  Language:Python1.3k64

• pulp-platform/axi_spi_slave

  Language:SystemVerilog2233

• drom/awesome-hdl

  Hardware Description Languages

  96295