elhep/AFCZ

Clocking tree

Closed this issue · 13 comments

kaolpr commented

There are several issues regarding clocking tree for AFCZ:

  • it is quite complex what makes it not really straightforward to use,
  • CERN has some requirements, that seem not to be met at the moment (will be discussed in the following comments to this issue)
  • some unification with AFC4 clocking tree may be considered (taking into account presence of SoC)

As a starting point for the discussion let's take a diagram (hopefully accurate) of the current AFCZ clocking tree:

AFCZ1v1_Clocking_rev0

If one wants to modify this diagram yEd source is here.

gkasprow commented

I would get rid of:
Si5324 - it will be replaced by DDMTD anyway
SY89540 and replace it by assembly option as in AFCv4
TCLKC and TCLKD optionally as an assembly option or not use at all.

kaolpr commented

Rev 1:

  • I believe it includes CERN suggestions
  • FMC clocking unified with AFCv4
  • RTM clocking for DESY Zone 3 Recommendation Class D1.4

AFCZ1v1_Clocking_rev1
If one wants to modify this diagram yEd source is here.
.

filipswit commented

May I start implementing Rev.1 to schematics?

kaolpr commented

It would be great if @gkasprow would approve it, but I think you can start implementing it.

You can swap clock matrix ports according to the layout constraints.

gkasprow commented

Looks good to me. Go ahead.

kaolpr commented

CERN reports that for their application a simultaneous use of:

  • GTP8-11_CLK connected to clock matrix and
  • MGT226 fed with WR clock.

Suggested resolution: connect CLK7 to MGT227 REFCLK0 with an assembly option to GTP4-7_CLK_IN/OUT.

filipswit commented

@kaolpr Could you please edit the diagram?

kaolpr commented

Yes, but after 18. I've uploaded the wrong file in the zip (PNG instead of diagram source) and I don't have access to that file right now.

kaolpr commented

AFCZ1v1_Clocking_rev2
Diagram source: AFCZ1v1_Clocking_rev2.zip

kaolpr commented
  • Invalid CLK11 connection
    image
  • Swapped FMC2_GBTCLK0_M2C with FMC2_GBTCLK1_M2C (connected to wrong MGT clocks)
  • Don't think we really need control buffer to AMC_TCLK and uFL connector. They can be always-on.

There are also couple of missing assembly options, but these are still to be defined.

Why do you use Undefined values of resistors in some places?

filipswit commented

Swapped FMC2_GBTCLK0_M2C with FMC2_GBTCLK1_M2C (connected to wrong MGT clocks)

Can we leave it as is? It's already routed on pcb? If not I'll swap it.

Undefined parts are some leavings from V1.0 - will be changed to 0R with variants

kaolpr commented

Yeah, we can keep it swapped.

kaolpr commented

One remark for routing - clock matrix ports can be assigned in a way that would be easier to route.