Pinned Repositories
Accelerating-CNN-with-FPGA
This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.
Accelerating-Quantized-CNN-Inference-on-FPGA
Accelerating-Quantized-CNN-Inference-on-FPGA(RTL)
CNN-FPGA
使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用
CNN_for_SLR
A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.
CNN_FPGA
verilog CNN generator for FPGA
cnn_open
A hardware implementation of CNN, written by Verilog and synthesized on FPGA
CNNAF-CNN-Accelerator
CNN-Accelerator based on FPGA developed by verilog HDL.
convolution_network_on_FPGA
CNN acceleration on virtex-7 FPGA with verilog HDL
FPGA-Accelerator-for-AES-LeNet-VGG16
FPGA/AES/LeNet/VGG16
fpga-NN-acceleration
Project folder for ENGR315 final project, accelerating a Python neural network with a Digilent PYNQ-Z1 board.
elicao's Repositories
elicao/fpga-NN-acceleration
Project folder for ENGR315 final project, accelerating a Python neural network with a Digilent PYNQ-Z1 board.
elicao/Accelerating-CNN-with-FPGA
This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.
elicao/Accelerating-Quantized-CNN-Inference-on-FPGA
Accelerating-Quantized-CNN-Inference-on-FPGA(RTL)
elicao/CNN-FPGA
使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用
elicao/CNN_for_SLR
A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.
elicao/CNN_FPGA
verilog CNN generator for FPGA
elicao/cnn_open
A hardware implementation of CNN, written by Verilog and synthesized on FPGA
elicao/CNNAF-CNN-Accelerator
CNN-Accelerator based on FPGA developed by verilog HDL.
elicao/convolution_network_on_FPGA
CNN acceleration on virtex-7 FPGA with verilog HDL
elicao/FPGA-Accelerator-for-AES-LeNet-VGG16
FPGA/AES/LeNet/VGG16
elicao/FPGA_Based_CNN
FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.
elicao/FPGA_NEURAL_NETWORK_ACCELERATION
This system accelerates a neural network made to recognize handwritten digits from an original time per sample of 200ms by 300x to a time of 0.66ms per sample.
elicao/hdl
HDL libraries and projects
elicao/lenet5_hls
FPGA Accelerator for CNN using Vivado HLS
elicao/PipeCNN
An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
elicao/TF2
An Open Source Deep Learning Inference Engine Based on FPGA
elicao/verilog-ethernet
Verilog Ethernet components for FPGA implementation
elicao/zynqnet
Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"