EM Microelectronic-US Inc.

binutils-gdb

A mirror of the upstream binutils-gdb repository for ARC specific work

core-v-docs

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

cpp-optparse

Python's excellent OptionParser in C++

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

elf2mif

Utility to convert an ELF file into a Memory Initialization File (MIF)

ELFIO

ELFIO - ELF (Executable and Linkable Format) reader and producer implemented as a header only C++ library

gcc

The development tree for GCC for the Synopsys DesignWare ARC processor family

pulp-riscv-binutils-gdb

riscv-dbg

RISC-V Debug Support for our PULP Cores

riscv-isa-sim

Spike, a RISC-V ISA Simulator

emmicro-us/binutils-gdb

A mirror of the upstream binutils-gdb repository for ARC specific work

emmicro-us/core-v-docs

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

emmicro-us/cpp-optparse

Python's excellent OptionParser in C++

emmicro-us/cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

emmicro-us/elf2mif

Utility to convert an ELF file into a Memory Initialization File (MIF)

emmicro-us/ELFIO

ELFIO - ELF (Executable and Linkable Format) reader and producer implemented as a header only C++ library

emmicro-us/gcc

The development tree for GCC for the Synopsys DesignWare ARC processor family

emmicro-us/pulp-riscv-binutils-gdb

emmicro-us/riscv-dbg

RISC-V Debug Support for our PULP Cores

emmicro-us/riscv-isa-sim

Spike, a RISC-V ISA Simulator

emmicro-us/toolchain

Repository containing releases of prebuilt GNU toolchains for DesignWare ARC Processors from Synopsys (available from 'releases' link below). The repository itself contains all the scripts required to build the GNU toolchain. Toolchain documentation available at https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/wiki . Processor Information available at