emrii

darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

DPRAM-Design-and-UVM-based-Verification

RTL design for a DUAL-PORT RAM and a UVM based testbench for functional verification. This project was undertaken to gain familiarity with UVM constructs.

Electronic-Ticket-Vending-Machine

This is a design for an electronic vending machine and a verilog based simulation testbench for its verification.

FIFO-Asynchronous

Interrupt_Controller

An 8 input interrupt controller written in Verilog.

ip-cores

A huge collection of VHDL/Verilog open-source IP cores scraped from the web

riscv-dv

Random instruction generator for RISC-V processor verification

verilog

Repository for basic (and not so basic) Verilog blocks with high re-use potential

verilog-file-parser

This automated script will parse through a verilog file RTL code and identify the module, its ports and parametrs. The path to the file should be given as an arguement on the command line, the result will be stored in a new file named 'LOG<name_of_module>.text'

emrii/DPRAM-Design-and-UVM-based-Verification

RTL design for a DUAL-PORT RAM and a UVM based testbench for functional verification. This project was undertaken to gain familiarity with UVM constructs.

emrii/verilog-file-parser

This automated script will parse through a verilog file RTL code and identify the module, its ports and parametrs. The path to the file should be given as an arguement on the command line, the result will be stored in a new file named 'LOG<name_of_module>.text'

emrii/darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

emrii/Electronic-Ticket-Vending-Machine

This is a design for an electronic vending machine and a verilog based simulation testbench for its verification.

emrii/FIFO-Asynchronous

emrii/Interrupt_Controller

An 8 input interrupt controller written in Verilog.

emrii/ip-cores

A huge collection of VHDL/Verilog open-source IP cores scraped from the web

emrii/riscv-dv

Random instruction generator for RISC-V processor verification

emrii/verilog

Repository for basic (and not so basic) Verilog blocks with high re-use potential