Could not create pin 'G0' for module 'top_module' with ID 1:

[thud06]

I am trying to load the ISCAS 89 Benchmarks. I am receiving the error:

[/home/user/Desktop/HAL/hal/src/netlist/module.cpp:816] could not create pin 'G0' for module 'top_module' with ID 1: net 'G0' with ID 5 is neither an input nor an output

The s27.v benchmark is shown below:

module s27(VDD,CK,G0,G1,G17,G2,G3);
input VDD,CK,G0,G1,G2,G3;
output G17;

  wire G5,G10,G6,G11,G7,G13,G14,G8,G15,G12,G16,G9;

  FD1 DFF_0(CK,G5,G10);
  FD1 DFF_1(CK,G6,G11);
  FD1 DFF_2(CK,G7,G13);
  IV  NOT_0(G14,G0);
  IV  NOT_1(G17,G11);
  AN2 AND2_0(G8,G14,G6);
  OR2 OR2_0(G15,G12,G8);
  OR2 OR2_1(G16,G3,G8);
  ND2 NAND2_0(G9,G16,G15);
  NR2 NOR2_0(G10,G14,G11);
  NR2 NOR2_1(G11,G5,G9);
  NR2 NOR2_2(G12,G1,G7);
  NR2 NOR2_3(G13,G2,G12);

endmodule

I was wondering what the fix for this would be ?

Thanks

[joern274]

@thud06 : Although you did not mention which gate library you are using I am guessing it was lsi_10k since I can reproduce your error message when I try to parse the netlist above with that one.

The point is that the pin order in your netlist does not match the pin order given in the gate library. The solution would be to adjust the pin order in either of the two.

Adjusting the netlist would look like this:

module s27(VDD,CK,G0,G1,G17,G2,G3);
input VDD,CK,G0,G1,G2,G3;
output G17;

  wire G5,G10,G6,G11,G7,G13,G14,G8,G15,G12,G16,G9;

  FD1 DFF_0(G5,CK,G10);
  FD1 DFF_1(G6,CK,G11);
  FD1 DFF_2(G7,CK,G13);
  IV  NOT_0(G0,G14);
  IV  NOT_1(G11,G17);
  AN2 AND2_0(G14,G6,G8);
  OR2 OR2_0(G12,G8,G15);
  OR2 OR2_1(G3,G8,G16);
  ND2 NAND2_0(G16,G15,G9);
  NR2 NOR2_0(G14,G11,G10);
  NR2 NOR2_1(G5,G9,G11);
  NR2 NOR2_2(G1,G7,G12);
  NR2 NOR2_3(G2,G12,G13);

endmodule

Please verify that you can parse and display the modified netlist using the lsi_10k gate library.