netlist

emsec/hal

HAL – The Hardware Analyzer

google/pcbdl

PCB Design Language: A programming way to design schematics.

circuitgraph/circuitgraph

Tools for working with circuits as graphs in python

najaeda/naja

Structural Netlist API (and more) for EDA post synthesis flow development

byuccl/spydrnet

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

electron-lang/electron

A mixed signal netlist language (pre-alpha)

aaanthonyyy/CircuitNet

A hand-drawn schematic sketch recognizer and converter. Three-Step pipeline: Component detection using traditional image processing; Component classification using a custom trained CNN; Schematic generation using a proprietary generation algorithm.

najaeda/naja-verilog

A standalone structural (gate-level) verilog parser

jimwang99/parser-for-chip-design

A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).

SpiceSharp/SpiceSharpParser

SPICE netlists parser for .NET

arasgungore/netlist-solver

A MATLAB project that uses modified nodal analysis to calculate the node voltages of any analog circuit.

ganeshgore/spydrnet-physical

This is a SpyDrNet Plugin for a physical design related transformations

akashlevy/pyxbar

Python tools for generating and testing SPICE netlists/waveforms involving crossbar memory arrays in various configurations

kailiuXD/xdcom

This is a demo for still image compression application

emsec/hal-benchmarks

Benchmark suite for HAL

FPGAsm/FPGAsm

A low-level hierarchical netlist assembler for FPGAs

byuccl/spydrnet-tmr

TMR utilities for the SpyDrNet project

SinaKarvandi/hardware-design-stack

The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

pablov55/Beginner-s-Guide-to-KiCad

This guide will teach you all the basics of KiCad from schematic building to PCB design. It will also teach you how to add libraries, create your own symbols & footprints, export the drill and gerber files, and many more tips to get you started on your KiCad journey!

jvestman/skimibowi

SKiDL Microcontroller Board Wizard

CIDARLAB/MINT

LCSR-lab/MODNET

MODNET (MODify NETlist): VHDL/Verilog Fault Injection system

shishir-dey/vhdl-samples

A comprehensive collection of VHDL designs for digital circuits, organized by category and featuring a complete test suite with automated CI/CD

BUAA-CLab/CircuitMind

The code about TC-Bench and CircuitMind

chmod775/trace

Electronic PCB Programmig Language: Create an Electronic Netlist and Schematic using JavaScript and limitless automations.

circuitgraph/circuitsim

Perform gate-level simulations from python

amfl/short-circuit

tile-based digital logic sandbox

firechip/pads-layout-parser

Library for parsing netlists in the PADS Layout ASCII format (`.asc` files). It provides a structured object representation of the netlist data, making it easy to process and convert to other formats like the Yosys JSON format used for circuit analysis and visualization.

jamestiotio/compstruct

SUTD 2020 50.002 Computation Structures Code Dump

JensRestemeier/EdifTests

A few experiments using the SpyDrNet netlist library.

SubZer0811/BE2SIM

This repository contains a python script that converts a Boolean Expression to a .SIM file (circuit netlist description).

arhamhashmi01/openlane-verification

This repository offers a compact design verification flow using OpenLANE. Scripts cover synthesis correctness, functional and power verification, DRC/LVS, timing analysis, and reliability checks. Contributions are welcome.

DevinduDh/LTspice-projects

LTSpice projects

FEntwumS/FEntwumS.NetlistViewer

An interactive netlist viewer, powered by GHDL, yosys and Avalonia

tscircuit/circuit-json-to-readable-netlist

Convert Circuit JSON into a readable netlist suitable for input to AI