byuccl/spydrnet-tmr

Issues

• pip install issues

  #34 opened 5 months ago by AEW2015
  1

• Some logical doubts in find_voter_insertion_points.py

  #33 opened 9 months ago by zywbjj
  0

• Move Tests and Example Netlists Out of the Main Package

  #32 opened a year ago by jacobdbrown4
  0

• Code Formatting

  #31 opened a year ago by jacobdbrown4
  0

• Verilog Netlist Issues

  #16 opened a year ago by emonlux
  1

• Updating os.path to pathlib

  #30 opened a year ago by emonlux
  0

• Yosys to F4PGA examples not working

  #29 opened a year ago by emonlux
  0

• Feedback folding for verilog netlists

  #26 opened a year ago by emonlux
  2

• Add bigger designs to DRC tests

  #3 opened 3 years ago by benglines
  1

• Add configuration file

  #4 opened 3 years ago by benglines
  1

• Update Symbiflow name to f4pga

  #13 opened a year ago by jacobdbrown4
  1

• Can this TMR F4PGA example designs?

  #18 opened a year ago by AEW2015
  2

• pip install .

  #15 opened 2 years ago by emonlux
  1

• Make SpyDrNet TMR internals more generic

  #20 opened 2 years ago by jacobdbrown4
  0

• EDIF netlists are not reproducible

  #19 opened 2 years ago by gsmecher
  1

• Namespace Manager Bug

  #14 opened 2 years ago by emonlux
  1

• Finding Voters After Symbiflow Renames Primitives

  #11 opened 2 years ago by jacobdbrown4
  5

• Drop Support For Python 3.5

  #10 opened 2 years ago by jacobdbrown4
  2

• Doing TMR on an EBLIF netlist fails

  #9 opened 2 years ago by jacobdbrown4
  4

• Change logo to say 'SpyDrNet TMR' instead of 'SpyDrNet SHREC'

  #1 opened 3 years ago by jacobdbrown4
  2

• Investigate the use of a SpyDrNet plugin for TMR

  #8 opened 3 years ago by wirthlin
  0

• Add command line functionality

  #7 opened 3 years ago by benglines
  0

• Brainstorm for More DRC Checks

  #5 opened 3 years ago by jacobdbrown4
  1